Method and apparatus for improvements in chip manufacture and design
View Patent ↗A method of securing a bond pad in to a semiconductor chip having an upper top metal surface which includes one or more holes, the method comprising the steps of forming a passivation layer over the upper metal surface, which passivation layer has holes therein substantially corresponding to the or each hole in the upper metal layer and being substantially the same size or smaller than the holes in the upper metal layer; forming the bond pad over the passivation layer; characterised in that the step of forming the bond pad comprises introducing some of the material from the bond pad into the holes in the passivation layer and upper metal layer when forming the bond pad, securing the bond pad to the passivation layer by allowing said material to flow under the surface thereof and attach thereto without attaching to the upper metal layer to thereby form a securing means.
1. A method of securing a bond pad to a semiconductor chip having an upper metal layer which includes one or more holes, the method comprising the steps of:
forming a passivation layer over the upper metal layer, wherein the passivation layer has one or more holes therein, that overlies one or more holes in the upper metal layer and are substantially the same size or smaller than the one or more holes in the upper metal layer;
forming the bond pad over the passivation layer;
wherein forming the bond pad comprises introducing some of the material from the bond pad into the one or more holes in the passivation layer and upper metal layer when forming the bond pad, and allowing portions of the material of the bond pad to flow under the surface of the passivation layer and attach thereto without attaching to the upper metal layer to secure the bond pad to the passivation layer.
2. The method of claim 1 wherein the step of introducing the material comprises applying molten material onto the passivation layer such that molten material enters the one or more holes and flows along the underside of the passivation layer.
3. The method of claim 2 , wherein the step of forming the passivation layer comprises forming the passivation layer having the one or more holes which are smaller than the one or more holes in the metal layer.
4. The method of claim 2 , further comprising forming the one or more holes to be substantially rectilinear.
5. The method of claim 2 , further comprising forming the one or more holes to be substantially circular.
6. The method of claim 1 , wherein the step of forming the passivation layer comprises forming the passivation layer having holes which are smaller than the one or more holes in the metal layer.
7. The method of claim 1 , further comprising forming the one or more holes to be substantially rectilinear.
8. The method of claim 1 , further comprising forming the one or more holes to be substantially circular.
9. The method of claim 1 , wherein the step of forming the passivation layer comprises forming the passivation layer having the one or more holes which are smaller than the one or more holes in the metal layer.
10. The method of claim 1 , further comprising forming the one or more holes to be substantially rectilinear.
11. The method of claim 1 , further comprising forming the one or more holes to be substantially circular.
12. A semiconductor chip having an upper metal layer which includes one or more holes, the chip further comprising:
a passivation layer over the upper metal layer, wherein the passivation layer has one or more holes therein that overlies one or more holes of the upper metal layer and substantially the same size or smaller than the one or more holes of the upper metal layer; and
a bond pad formed over the passivation layer;
wherein the bond pad comprises a material that extends through the one or more holes in the passivation layer and upper metal layer wherein portions of the material extend along an underside of the passivation layer without attaching to the upper metal layer to secure the bond pad to the passivation layer.
13. The semiconductor chip of claim 12 , wherein the one or more holes in the passivation layer are smaller than the one or more holes in the upper metal layer.
14. The semiconductor chip of claim 13 , wherein the one or more holes is substantially rectilinear.
15. The semiconductor chip of claim 13 , wherein the one or more holes is substantially circular.
16. The semiconductor chip of claim 12 , wherein the one or more holes is substantially rectilinear.
17. The semiconductor chip of claim 12 , wherein the one or more holes is substantially circular.
18. The semiconductor chip of claim 12 , wherein the material is a molten material which enters the one or more holes and flows along the underside of the passivation layer.