Method of blocking a void during contact formation
View Patent ↗An electronic device can include conductive regions. A void can extend between different portions of an insulating layer. Different openings can intersect the void. A liner layer can substantially block the void, substantially preventing subsequently forming an electrical leakage path along the void. In one aspect, a stressor layer can be deposited over the conductive regions prior to forming the insulating layer. The liner layer can be formed over the stressor layer within the different openings through the insulating layer. In another aspect, an etch-stop layer can be formed over a silicide layer prior to forming the insulating layer. After removing a portion of the liner layer, a portion of the etch-stop layer can be removed to expose the silicide layer within the different openings. In yet another aspect, a nitride layer can lie between a substrate and the insulating layer and include a section of the openings.
1. A process of forming an electronic device comprising:
forming a first conductive region within a substrate corresponding to a first component;
forming a second conductive region within the substrate and adjacent to the first conductive region, wherein the second conductive region corresponds to a second component;
depositing a stressor layer including an insulating material over the first conductive region and the second conductive region;
forming a first insulating layer over the stressor layer, wherein forming the first insulating layer includes forming a void within the first insulating layer and wherein, from a top view, the void lies between the first conductive region and the second conductive region;
forming a first opening through a first portion of the first insulating layer and a second opening through a second portion of the first insulating layer, wherein:
the first portion overlies the first conductive region;
the second portion overlies the second conductive region;
the void connects the first opening and the second opening; and
the stressor layer lies between the first conductive region and a bottom of the first opening, and between the second conductive region and a bottom of the second opening;
forming a second insulating layer over the stressor layer within the first opening, the second opening, or any combination thereof, wherein forming the second insulating layer includes substantially blocking the void.
2. The process of claim 1 , wherein forming the stressor layer comprises depositing a silicon nitride.
3. The process of claim 2 , wherein removing a portion of the second insulating layer includes performing a blanket etch process.
4. The process of claim 2 , wherein forming the second insulating layer comprises depositing an oxide material.
5. The process of claim 1 , further comprising forming a silicide layer over the first conductive region, the second conductive region, or any combination thereof prior to forming the stressor layer, wherein the silicide layer includes nickel, cobalt, tungsten, or any combination thereof
6. The process of claim 5 , wherein depositing the stressor layer is performed after forming the silicide layer and before forming the second insulating layer.
7. The process of claim 1 , wherein:
forming the stressor layer includes depositing a nitrogen-containing insulating material; and
forming the second insulating layer includes depositing an oxygen-containing material
8. The process of claim 7 , wherein depositing the stressor layer includes depositing the stressor layer such that the stressor layer within the first opening has a compressive stress and the stressor layer within the second opening has a tensile stress.
9. The process of claim 1 , wherein:
forming the first conductive region within the substrate corresponding to the first component includes forming the first conductive region within the substrate corresponding to the first component wherein the first component includes a first transistor; and
forming a second conductive region within the substrate and adjacent to the first conductive region, wherein the second conductive region corresponds to a second component includes forming a second conductive region within the substrate and adjacent to the first conductive region, wherein the second conductive region corresponds to a second component, wherein the second component includes a second transistor.
10. A process of forming an electronic device comprising:
forming a first conductive region corresponding to a first component;
forming a second conductive region and adjacent to the first conductive region, wherein the second conductive region corresponds to a second component;
forming a silicide layer over the first conductive region and the second conductive region;
depositing an etch-stop layer over the silicide layer;
forming a first insulating layer over the etch-stop layer, wherein forming the first insulating layer includes forming a void within the first insulating layer, wherein, from a top view, the void extends between the first conductive region and the second conductive region;
forming a first opening through a first portion of the first insulating layer and a second opening though a second portion of the first insulating layer, wherein:
the first portion overlies the first conductive region;
the second portion overlies the second conductive region;
the void connects the first opening and the second opening; and
after forming the first and second opening, the etch-stop layer lies between the silicide layer and a bottom of the first opening, and between the silicide layer and a bottom of the second opening;
forming a second insulating layer within the first opening, the second opening, or any combination thereof wherein forming the second insulating layer includes substantially blocking the void, wherein the etch-stop layer lies between the second insulating layer and the silicide layer; and
removing portions of the etch-stop layer and the second insulating layer within the first and second openings to expose the first and second conductive regions, wherein after removing portions of the etch-stop layer and the second insulating layer, a remaining portion of the second insulating layer substantially blocks the void.
11. The process of claim 10 , wherein:
forming the etch-stop layer includes depositing silicon nitride; and
forming the second insulating layer includes depositing an oxide material.
12. The process of claim 10 , wherein forming the silicide layer includes forming the silicide layer including europium, nickel, titanium, ytterbium, yttrium or any combination thereof.
13. The process of claim 11 , wherein forming the first insulating layer including depositing the oxide material.
14. The process of claim 10 , further including depositing a conductive material within the first opening and the second opening after removing the portion of the etch-stop layer, wherein after depositing the conductive material substantially none of the conductive material lies within the void.
15. The process of claim 14 , further including removing a portion of the conductive material wherein after removing a portion of the conductive material, substantially none of the conductive material lies between the first opening and the second opening.
16. The process of claim 10 , wherein removing a portion of the second insulating layer includes performing a blanket etch process.
17. The process of claim 10 , wherein the first conductive region is an n-channel region and the second conductive region is a p-channel region.
18. The method of claim 10 , wherein forming the second insulating layer comprises forming the second insulating layer having a thickness that is at most ⅓ of a width of the first opening, the second opening, or both.
19. The method of claim 1 , wherein forming the second insulating layer comprises forming the second insulating layer having a thickness that is at most ⅓ of a width of the first opening, the second opening, or both.
20. The method of claim 4 , wherein forming the first insulating layer comprises depositing the oxide material.