IP Library Granted Patent US 7,649,234
Granted Patent B2
US 7,649,234 · App. 12/129,861 · Granted Jan 19, 2010

Semiconductor devices

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Quick Facts
Patent No.
US 7,649,234
App. No.
12/129,861
Granted
Jan 19, 2010
Kind
B2
Abstract

An embodiment of a semiconductor device includes a gate electrode overlying a substrate and a lightly doped epitaxial layer formed on the substrate. A high energy implant region forms a well in a source side of the lightly doped epitaxial layer. A self-aligned halo implant region is formed on a source side of the device and within the high energy well implant. An implant region on a drain side of the lightly doped epitaxial layer forms a gate overlapped LDD (GOLD). A doped region within the halo implant region forms a source. A doped region within the gate overlapped LDD (GOLD) forms a drain.

Claims (41)

1. A semiconductor device including a semiconductor substrate having a surface comprising:

a doped epitaxial layer formed on the surface of the substrate;

a gate electrode disposed overlying the doped epitaxial layer;

a first impurity doped region disposed within the doped epitaxial layer and partially offset from the gate electrode on a first side of the gate electrode, and implanted using a first type of doping;

a halo implant region disposed within the first impurity doped region and implanted using the first type of doping;

a gate overlapped lightly doped drain region disposed within the doped epitaxial layer on a second side of the gate electrode, and implanted using a second type of doping, wherein the second side is opposite the first side, and the second type of doping is opposite the first type of doping;

a source region formed in the halo implant region, wherein the halo implant region extends beyond the source region, at least partially under the gate electrode, and into a channel area between the source region and a drain region; and

a drain region formed in the gate overlapped lightly doped drain region, wherein the gate overlapped lightly doped drain region extends beyond the drain region, at least partially under the gate electrode, and into the channel area, and wherein the halo implant region and the gate overlapped lightly doped drain region are separated from each other.

2. The semiconductor device including a semiconductor substrate having a surface as claimed in claim 1 , wherein the doped epitaxial layer has a doping concentration of 2×10 15 /cm 3 .

3. The semiconductor device of claim 1 , wherein the first impurity doped region is a well region formed in the doped epitaxial layer and has a doping concentration in a range of 1×10 17 /cm 3 to 8×10 17 /cm 3 .

4. The semiconductor device of claim 1 , wherein the halo implant region has a doping concentration in a range of 5×10 18 /cm 3 to 6×10 18 /cm 3 .

5. The semiconductor device of claim 1 , wherein the gate overlapped lightly doped drain region has a doping concentration in a range of 1×10 18 /cm 3 to 5×10 18 /cm 3 .

6. The semiconductor device of claim 1 , wherein doping materials selected from the group consisting of germanium (Ge), arsenic (As), phosphorous (P), and boron (B) provide doping for the doped epitaxial layer, the first impurity doped region, the halo implant region, the gate overlapped lightly doped drain region, the source regions, and the drain region.

7. A semiconductor device including a semiconductor substrate having a surface comprising:

an epitaxial layer doped with a first type of doping material;

a first doped well on a source side of the substrate, wherein the first doped well is impurity doped with the first type of doping material;

a gate electrode overlying a surface of the substrate and having a gate dielectric formed therebetween;

a halo implant region formed in self alignment with the gate electrode on the source side of the substrate and implanted using an impurity ion of the first type of doping material at an angle greater than zero from an axis perpendicular to the surface of the substrate;

a lightly doped drain implant formed in self alignment with the gate electrode on a drain side of the substrate and impurity doped with a second type of doping material;

a source region in the halo implant region; and

a drain region in the lightly doped drain implant, wherein the halo implant region and the lightly doped drain implant extend beyond the source region and the drain region and into a channel area between the source region and the drain region.

8. The semiconductor device of claim 7 , wherein the first type of doping material includes ions that comprise a material selected from the group consisting of germanium (Ge), arsenic (As), phosphorous (P), and boron (B).

9. The semiconductor device of claim 7 , wherein the first doped well comprises boron implanted at an implant concentration of 1×10 15 /cm 3 .

10. The semiconductor device of claim 7 , further comprising:

a second doped well formed within a portion of the first doped well by chain implanting boron at energy of 15K to 500 KeV and at an implant concentration in a range of 1×10 17 /cm 3 to 2×10 18 /cm 3 .

11. The semiconductor device of claim 7 , wherein the halo implant region comprises boron implanted at an energy of 30 KeV and at an implant concentration in a range of 5×10 18 /cm 3 to 6×10 18 /cm 3 .

12. The semiconductor device of claim 7 , wherein the lightly doped drain implant comprises boron implanted at an energy of 30 KeV and at an implant concentration in a range of 1×10 18 /cm 3 to 5×10 18 /cm 3 .

13. A semiconductor device including a semiconductor substrate having a surface comprising:

a doped epitaxial layer on the surface of the substrate and doped with a first type of doping material;

a doped well of the first type of doping material in the doped epitaxial layer and on a source side of the substrate;

a gate electrode overlying a surface of the substrate and having a gate dielectric formed therebetween;

a halo implant region formed in self alignment with the gate electrode on the source side of the substrate and implanted using an impurity ion of the first type of doping material at an angle greater than zero from an axis perpendicular to the surface of the substrate;

a lightly doped drain implant formed in self alignment with the gate electrode on a drain side of the substrate and impurity doped with a second type of doping material;

an insulating spacer formed about the gate electrode;

a source region implanted in the halo implant region; and

a drain region implanted in the lightly doped drain implant, wherein the halo implant region and the lightly doped drain implant extend beyond the source region and the drain region and into a channel area between the source region and the drain region.

14. The semiconductor device of claim 13 , wherein the first type of doping material includes ions that comprise a material selected from the group consisting of germanium (Ge), arsenic (As), phosphorous (P), and boron (B).

15. The semiconductor device of claim 13 , wherein the doped epitaxial layer comprises boron deposited at a concentration of 2×10 14 to 2×10 15 /cm.

16. The semiconductor device of claim 13 , wherein the doped well comprises boron implanted at an energy of 30 KeV and at an implant concentration in a range of 1×10 17 /cm 3 to 2×10 18 /cm 3 .

17. The semiconductor device of claim 13 , wherein the halo implant region comprises boron implanted at an energy of 30 KeV and at an implant concentration in a range of 5×10 18 /cm 3 to 6×10 18 /cm 3 .

18. The semiconductor device of claim 13 , wherein the lightly doped drain implant comprises boron implanted at an energy of 30 KeV and at an implant concentration in a range of 1×10 18 /cm 3 to 5×10 18 /cm 3 .

Assignments (37)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
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To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
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To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
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