Semiconductor structure and method of manufacture
View Patent ↗A semiconductor structure ( 100 ) includes a substrate ( 110 ) having a first surface ( 111 ) with a mold lock feature ( 101 ). The semiconductor structure also includes a semiconductor chip ( 120 ) located over the first surface of the substrate. The semiconductor structure further includes an electrical isolator structure ( 340 ) located over the first surface of the substrate. The electrical isolator structure includes an electrical lead ( 341, 342 ) and an electrically insulative element ( 343 ) molded to the electrical lead. An optional portion ( 444 ) of the electrical isolator structure is located in the mold lock feature. The semiconductor structure additionally includes an adhesive element ( 450 ) located between and coupling the electrical isolator structure and the first surface of the substrate.
1. A semiconductor structure comprising:
a substrate having a first surface with a mold lock feature;
a semiconductor chip located over the first surface of the substrate;
an electrical isolator structure located over the first surface of the substrate, wherein the electrical isolator structure comprises an electrical lead and an electrically insulative element molded to the electrical lead; and
an adhesive element located between and coupling the electrical isolator structure and the first surface of the substrate,
wherein:
a portion of the electrical lead is located over a portion of the mold lock feature.
2. The semiconductor structure of claim 1 wherein:
a portion of the adhesive element is located in the mold lock feature.
3. A semiconductor structure comprising:
a substrate having a first surface with a mold lock feature;
a semiconductor chip located over the first surface of the substrate;
an electrical isolator structure located over the first surface of the substrate, wherein the electrical isolator structure comprises an electrical lead and an electrically insulative element; and
an adhesive element located between and coupling the electrical isolator structure and the first surface of the substrate,
wherein:
a portion of the electrical isolator structure snaps together with the mold lock feature.
4. The semiconductor structure of claim 3 wherein:
a portion of the adhesive element is located in the mold lock feature.
5. A semiconductor structure comprising:
a substrate having a first surface with a mold lock feature;
a semiconductor chip located over the first surface of the substrate;
an electrical isolator structure located over the first surface of the substrate, wherein the electrical isolator structure comprises an electrical lead and an electrically insulative element; and
an adhesive element located between and coupling the electrical isolator structure and the first surface of the substrate,
wherein:
a portion of the electrical isolator structure mates with the mold lock feature.
6. The semiconductor structure of claim 5 wherein:
a portion of the adhesive element is located in the mold lock feature.
7. A semiconductor structure comprising:
a substrate having a first surface with a mold lock feature;
a semiconductor chip located over the first surface of the substrate;
an electrical isolator structure located over the first surface of the substrate, wherein the electrical isolator structure comprises an electrical lead and an electrically insulative element; and
an adhesive element located between and coupling the electrical isolator structure and the first surface of the substrate,
wherein:
a portion of the electrical isolator structure is located in the mold lock feature; and
the portion of the electrical isolator structure is conformal to the mold lock feature.
8. The semiconductor structure of claim 1 wherein:
the mold lock feature is a recess.
9. A semiconductor structure comprising:
a substrate having a first surface with a mold lock feature;
a semiconductor chip located over the first surface of the substrate;
an electrical isolator structure located over the first surface of the substrate, wherein the electrical isolator structure comprises an electrical lead and an electrically insulative element; and
an adhesive element located between and coupling the electrical isolator structure and the first surface of the substrate,
wherein:
the mold lock feature is a recess;
a portion of the electrical isolator structure is located in the mold lock feature; and
the portion of the electrical isolator structure is a protrusion.
10. A semiconductor packaging system comprising:
a flange comprised of an electrically conductive material and having a first surface with at least one mold lock recess;
at least one semiconductor chip having at least one semiconductor device located over and electrically coupled to the first surface of the flange, wherein the at least one semiconductor device is an active device;
at least one matching element located over the first surface of the flange;
an adhesive element coupling the at least one semiconductor chip to the first surface of the flange;
a frame structure comprised of at least two electrical leads and an organic-based, electrically insulative element, wherein a first portion of the organic-based, electrically insulative element is located over the first surface and mated with the at least one mold lock recess;
an epoxy element located between and coupling the frame structure and the first surface of the flange, wherein a first portion of the epoxy element is located in the at least one mold lock recess; and
interconnect structures electrically coupling the at least one semiconductor device and the at least one matching element to the at least two electrical leads; and
a lid located over the flange and the frame structure to at least gross leak seal the at least one semiconductor chip and the at least one matching element therein.
11. The semiconductor packaging system of claim 10 wherein:
the at least one mold lock recess is a mechanical reinforcement of an interface between the frame structure and the flange.
12. The semiconductor packaging system of claim 10 wherein:
the first surface of the flange has a first alignment recess;
the organic-based, electrically insulative element has a second portion located in the first alignment recess; and
the first alignment recess aligns together the frame structure and the flange.
13. The semiconductor packaging system of claim 12 wherein:
the epoxy element has a second portion located in the first alignment recess.
14. The semiconductor packaging system of claim 12 wherein:
the first surface of the flange has a second alignment recess;
the organic-based, electrically insulative element has a third portion located in the second alignment recess; and
the first and second alignment recesses align together the frame structure and the flange.
15. The semiconductor packaging system of claim 14 wherein:
the first surface of the flange has a first side and a second side adjacent to the first side; and
the first alignment recess is located at the first side of the first surface and forms a portion of an edge of the first surface; and
the second alignment recess is located at the second side of the first surface.
16. The semiconductor packaging system of claim 15 wherein:
the epoxy element has a second portion located in the first alignment recess; and
the epoxy element has a third portion located in the second alignment recess.
17. The semiconductor packaging system of claim 10 wherein:
the first surface of the flange has an epoxy dam recess.
18. The semiconductor packaging system of claim 17 wherein:
the epoxy dam recess is located between the at least one mold lock recess and a center of the flange.
19. The semiconductor packaging system of claim 17 further comprising:
the first surface of the flange has a first alignment recess;
the organic-based, electrically insulative element has a second portion located in the first alignment recess; and
the first alignment recess aligns together the frame structure and the flange.
20. The semiconductor packaging system of claim 19 wherein:
the first alignment recess forms a portion of an edge of the first surface of the flange.
21. The semiconductor packaging system of claim 10 wherein:
the first surface of the flange has a first portion comprising a solderable surface;
the at least two semiconductor chips are soldered to the first portion of the first surface of the flange by the adhesive element;
the at least one mold lock recess is located between the first portion of the flange and an edge of the first surface of the flange;
the at least one mold lock recess is devoid of a solderable surface; and
a second portion of the first surface of the flange located between the first portion of the first surface of the flange and the edge of the first portion of the first surface of the flange comprises a non-solderable surface.
22. The semiconductor structure of claim 1 further comprising:
one or more wire bonds electrically coupling the semiconductor chip to the electrical lead.
23. The semiconductor structure of claim 1 wherein:
the substrate further comprises an alignment recess.
24. The semiconductor structure of claim 5 wherein:
the substrate further comprises an alignment recess.
25. The semiconductor structure of claim 7 further comprising:
the substrate further comprises an alignment recess.
26. The semiconductor structure of claim 9 wherein:
the substrate further comprises an alignment recess.
27. The semiconductor structure of claim 9 wherein:
the electrical isolator structure comprises at least one of a plastic polymer, a thermoplastic, and a thermoset plastic.