Electronic device and method
View Patent ↗A current boost module receives a signal from the input and the output of a buffer to determine whether the buffer is transitioning between logic states. When the buffer is transitioning, a boost current is provided to a load connected to the buffer output to supplement the current from buffer output, thereby facilitating transition of a signal at the load. The current boost module can shut down the boost current before the signal at the load completes its transition from one logic state to the other.
1. An electronic device comprising:
a buffer comprising an input and an output;
an interconnect coupled to the output of the buffer; and
a current boost module comprising a first input coupled to the buffer input, a second input coupled to the interconnect, a third input to receive an adjustable threshold voltage, and an output coupled to the interconnect, the current boost module to detect when the buffer is transitioning between logic states based on the adjustable threshold voltage and to provide a boost current in response to detecting a signal transition between logic states at the interconnect has not completed to increase a rate of the signal transition at the interconnect in response to detecting the signal transition.
2. The device as in claim 1 , further comprising a receive/drive device comprising an input coupled to the interconnect, and an output, the receive/drive device configured to produce an output signal at its output responsive to a signal at its input.
3. The device as in claim 2 , wherein the input of the receive/drive device is responsive to a voltage that varies between 0 volts and 1.3 volts.
4. The device as in claim 3 , wherein the receive/drive device is a data bus driver.
5. The device as in claim 3 , further comprising one of a video or audio module coupled to the output of the receive/drive device.
6. The device as in claim 3 , wherein a threshold voltage of the receive/drive device is between approximately 0.5 volts and 0.7 volts.
7. The device of claim 1 , wherein the current boost module is configured to detect when the buffer is transitioning between logic states based on the adjustable threshold voltage based on a comparison of the adjustable threshold voltage to a voltage at the interconnect.
8. The device of claim 1 , wherein the current boost module further comprises:
a first comparator comprising a first input coupled to the interconnect, a second input configured to receive the threshold voltage, and an output; and
a second comparator comprising a first input coupled to the interconnect, a second input configured to receive the threshold voltage, and an output, wherein the current boost module provides the boost current based on the output of the first comparator and the output of the second comparator.
9. The device of claim 8 , wherein the current boost module further comprises:
a first transistor of a first connectivity type comprising a first current electrode coupled to a voltage reference, a second current electrode, and a control electrode coupled to the input of the buffer;
a second transistor of the first connectivity type comprising a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to the interconnect, and a control electrode coupled to the output of the first comparator;
a third transistor of a second connectivity type comprising a first current electrode coupled to the interconnect, a second current electrode, and a control electrode coupled to the output of the second comparator; and
a fourth transistor of the second connectivity type comprising a first current electrode coupled to the second current electrode of the third transistor, a second current electrode coupled to a second voltage reference, and a control electrode coupled to the input of the buffer.
10. A method for reducing switching delay of an electronic device comprising:
detecting a first signal at an input of a buffer;
detecting a second signal at an output of the buffer;
based on a comparison of the second signal to an adjustable threshold voltage, providing a boost current to an interconnect coupled to the output of the buffer when it is determined in response to detecting the first and second signal that the buffer is in transition between logic states, the boost current to increase a rate of the transition.
11. The method of claim 10 , wherein providing the boost current occurs only during a portion of the buffer's transition between logic states.
12. The method of claim 10 , wherein the input signal has a voltage range from between 0 volts and 1.3 volts.
13. The method of claim 10 , wherein providing the boost current occurs between when an input signal on the input of the buffer is received and when an output of the buffer transitions to a different state.
14. The method of claim 13 , wherein providing the current boost increases a slew rate at the interconnect to reduce a signal transition delay between the input of the buffer and a corresponding signal transition at the output of a device having an input coupled to the interconnect.
15. The method of claim 10 , wherein providing the boost current increases a slew rate at the interconnect by more than approximately 0.5V/ns.
16. The method of claim 10 , further comprising transmitting data over a multi-destination data bus via a receive/drive device that is responsive to a signal at the interconnect.
17. The method of claim 10 , wherein boosting the current only occurs during a portion of the second signal's transition.
18. The method of claim 17 , wherein the portion of the second signal's transition during which boosting the current occurs is based upon a voltage threshold of a transistor.