Charge storage structure formation in transistor with vertical channel region
View Patent ↗A semiconductor device includes a semiconductor structure having a first sidewall. A vertical channel region is formed in the semiconductor structure along the first sidewall between a first current electrode region and a second current electrode region. First and second charge storage structures are formed adjacent to the first sidewall in openings of a dielectric layer. The first and second charge storage structures are electrically isolated from each other and from the semiconductor structure. A control electrode is formed adjacent to the first sidewall. In another embodiment, third and fourth charge storage structures may be formed adjacent to a second sidewall of the semiconductor structure in openings of a dielectric layer.
1. A semiconductor device, comprising:
a semiconductor structure having a first sidewall and a channel region, wherein a portion of said channel region is disposed along said first sidewall, and wherein the channel region is disposed between first and second current electrode regions;
first and second charge storage structures disposed adjacent to the first sidewall and adjacent to the portion of the channel region disposed along the first sidewall, wherein the first and second charge storage structures are electrically isolated from each other and from the semiconductor structure;
a first control electrode formed adjacent to the first sidewall;
a first dielectric layer disposed between the control electrode and the first sidewall;
a second dielectric layer disposed between the control electrode and the first dielectric layer; and
a third dielectric layer disposed between the first dielectric layer and the second dielectric layer;
wherein a portion of the third dielectric layer is laterally disposed between the first charge storage structure and the second charge storage structure; wherein the first dielectric layer has a first lateral length L 1 in a first direction along the first sidewall, the second dielectric layer has a second lateral length L 2 in a direction parallel to the first direction, and the third dielectric layer has a third lateral length L 3 in a direction parallel to the first direction; and wherein L 3 <L 1 , L 2 .
2. The semiconductor device of claim 1 , wherein the semiconductor device further comprises:
third and fourth charge storage structures located adjacent to a second sidewall of said semiconductor structure, wherein the third and fourth charge storage structures are electrically isolated from each other and are electrically isolated from the semiconductor structure.
3. The semiconductor device of claim 2 , further comprising a second control electrode disposed adjacent to the second sidewall, wherein the second control electrode is electrically independent from the first control electrode.
4. The semiconductor device of claim 2 , wherein said first and second sidewalls form opposing surfaces of the semiconductor device.
5. The semiconductor device of claim 1 , wherein each of the first and second charge storage structures comprises germanium.
6. The semiconductor device of claim 1 , further comprising:
a first dielectric layer formed adjacent to the first sidewall;
a second dielectric layer formed adjacent to the first dielectric layer; and
a third dielectric layer formed adjacent to the second dielectric layer;
wherein the first, second, and third dielectric layers provide electrical isolation for the first charge storage structure and the second charge storage structure;
wherein the second dielectric layer has first and second openings therein, and wherein the first charge storage structure is formed within the first opening and the second charge storage structure is formed within the second opening.
7. The semiconductor device of claim 6 , wherein the first and second dielectric layers respectively comprise first and second distinct materials.
8. The semiconductor device of claim 1 , wherein the first and second charge storage structures are floating gate charge storage structures.
9. The semiconductor device of claim 8 , wherein said semiconductor device is a non-volatile memory cell.
10. The semiconductor device of claim 1 , wherein the semiconductor structure is a semiconductor fin structure.
11. The semiconductor device of claim 10 . wherein the fin structure is capped with a fourth dielectric layer.
12. The semiconductor device of claim 1 , wherein the first and second charge storage structures comprise a material selected from the group consisting of polysilicon, metal, silicon, germanium, and polysilicon germanium.
13. The semiconductor device of claim 12 , wherein the first and second charge storage structures comprise a metal.
14. The semiconductor device of claim 12 , wherein the first and second charge storage structures comprise polysilicon.
15. The semiconductor device of claim 12 , wherein the first and second charge storage structures comprise polysilicon germanium.
16. The semiconductor device of claim 1 , wherein the first and second charge storage structures are formed within a layer having a thickness within the range of 20 Å to 70 Å.
17. The semiconductor device of claim 1 , wherein the first dielectric layer has a thickness within the range of 10 Å to 100 Å.
18. The semiconductor device of claim 1 , wherein the third dielectric layer comprises a high-k material.
19. The semiconductor device of claim 1 , wherein the fourth dielectric layer comprises silicon nitride.
20. The semiconductor device of claim 1 , wherein said semiconductor structure is disposed on a dielectric substrate.
21. A semiconductor device, comprising:
a semiconductor structure formed on an SOI wafer and having a first sidewall and a channel region, wherein the channel region is disposed between a first current electrode region and a second current electrode region, and wherein a portion of the channel region is disposed along the first sidewall;
first and second charge storage structures, wherein the first charge storage structure is disposed adjacent to the first sidewall and adjacent to the portion of the channel region located along the first sidewall, and wherein the first charge storage structure and the second charge storage structure comprise electrically conductive materials having thicknesses within the range of about 15 Å to about 50 Å and which are electrically isolated from each other and from the semiconductor structure; and
a control electrode formed adjacent to the first sidewall.
22. The semiconductor device of claim 21 , wherein each of the first and second charge storage structures comprises a charge carrier disposed in an electrically conductive medium.
23. The semiconductor device of claim 22 , wherein the electrically conductive medium comprises a material selected from the group consisting of polysilicon and metal.
24. The semiconductor device of claim 21 , wherein each of the first and second charge storage structures is a floating gate.