Electronic apparatus interconnect routing and interconnect routing method for minimizing parasitic resistance
View Patent ↗Method and apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect ( 40, 42, 44 ) configured to couple to a first region of the substrate, a first gate ( 22, 24, 26, 28 ) coupled to the first interconnect and configured to receive a first differential input, a second interconnect ( 30, 32, 34, 36, 38 ) parallel to the first interconnect and configured to couple to a second region of the substrate, and a second gate ( 20 ) coupled to the second interconnect and configured to receive a second differential input. The first gate is parallel to the first interconnect, and the second gate is parallel to the second interconnect.
1. An electronic apparatus formed on a substrate, the electronic apparatus comprising:
a first set of polysilicon fingers coupled to the substrate and configured to receive a first differential input signal;
a first interconnect formed of a first metal layer and coupled to said first set of polysilicon fingers and having a first lengthwise axis;
a second set of polysilicon fingers coupled to the substrate and interdigitated with the first set of polysilicon fingers, wherein the second set of polysilicon fingers is configured to receive a second differential input signal; and
a second interconnect formed of a second metal layer that is a different layer from the first metal layer, the second interconnect being coupled to said second set of polysilicon fingers and having a second lengthwise axis, said second lengthwise axis parallel to said first lengthwise axis, and said first lengthwise axis different from said second lengthwise axis;
a third interconnect coupled to said first interconnect and said first set of polysilicon fingers, said third interconnect having a third lengthwise axis that is perpendicular to said first lengthwise axis, wherein the third interconnect is formed of a different layer from the second metal layer;
a fourth interconnect coupled to said second interconnect and said second set of polysilicon fingers, said fourth interconnect having a fourth lengthwise axis that is perpendicular to said second lengthwise axis; and
an air bridge between said third interconnect and said second interconnect.
2. An electronic apparatus formed on a substrate, the electronic apparatus comprising:
a first set of polysilicon fingers coupled to the substrate and configured to receive a first differential input signal;
a first interconnect formed of a first metal layer and coupled to said first set of polysilicon fingers and having a first lengthwise axis;
a second set of polysilicon fingers coupled to the substrate and interdigitated with the first set of polysilicon fingers, wherein the second set of polysilicon fingers is configured to receive a second differential input signal; and
a second interconnect formed of a second metal layer that is a different layer from the first metal layer, the second interconnect being coupled to said second set of polysilicon fingers and having a second lengthwise axis, said second lengthwise axis parallel to said first lengthwise axis, and said first lengthwise axis different from said second lengthwise axis;
a third interconnect coupled to said first interconnect and said first set of polysilicon fingers, said third interconnect having a third lengthwise axis that is perpendicular to said first lengthwise axis;
a fourth interconnect coupled to said second interconnect and said second set of polysilicon fingers, said fourth interconnect having a fourth lengthwise axis that is perpendicular to said second lengthwise axis, said second interconnect located on a penultimate layer of said plurality of layers, and said third interconnect located on a top-most layer of said plurality of layers; and
an air bridge between said third interconnect and said second interconnect.
3. An electronic apparatus formed on a substrate, the electronic apparatus comprising:
a first set of polysilicon fingers coupled to the substrate and configured to receive a first differential input signal;
a first interconnect formed of a first metal layer and coupled to said first set of polysilicon fingers and having a first lengthwise axis;
a second set of polysilicon fingers coupled to the substrate and interdigitated with the first set of polysilicon fingers, wherein the second set of polysilicon fingers is configured to receive a second differential input signal; and
a second interconnect formed of a second metal layer that is a different layer from the first metal layer, the second interconnect being coupled to said second set of polysilicon fingers and having a second lengthwise axis, said second lengthwise axis parallel to said first lengthwise axis, and said first lengthwise axis different from said second lengthwise axis;
a third interconnect coupled to said first interconnect and said first set of polysilicon fingers, said third interconnect having a third lengthwise axis that is perpendicular to said first lengthwise axis, wherein the first interconnect and the third interconnect form portions of a first plurality of stacked interconnects that is coupled to said first set of polysilicon fingers, and said third interconnect a top-most stacked interconnect of said first plurality of stacked interconnects; and
a fourth interconnect coupled to said second interconnect and said second set of polysilicon fingers, said fourth interconnect having a fourth lengthwise axis that is perpendicular to said second lengthwise axis, wherein the second interconnect and the fourth interconnect form portions of a second plurality of stacked interconnects that is coupled to said second set of polysilicon fingers, and said second interconnect a top-most stacked interconnect of said second plurality of stacked interconnects.
4. An electronic apparatus formed on a substrate, the electronic apparatus comprising:
a first set of polysilicon fingers coupled to the substrate and configured to receive a first differential input signal;
a first interconnect formed of a first metal layer and coupled to said first set of polysilicon fingers and having a first lengthwise axis;
a second set of polysilicon fingers coupled to the substrate and interdigitated with the first set of polysilicon fingers, wherein the second set of polysilicon fingers is configured to receive a second differential input signal;
a second interconnect formed of a second metal layer that is different from the first metal layer, the second interconnect being coupled to said second set of polysilicon fingers and having a second lengthwise axis, said second lengthwise axis parallel to said first lengthwise axis, and said first lengthwise axis different from said second lengthwise axis;
a third interconnect coupled to said first interconnect and said first set of polysilicon fingers, said third interconnect having a third lengthwise axis that is perpendicular to said first lengthwise axis, wherein the third interconnect is formed of a different layer from the second metal layer; and
an air bridge between said third interconnect and said second interconnect.
5. An electronic apparatus according to claim 4 , wherein the first, second, and third interconnects are formed of a plurality of layers, said second interconnect is located on a penultimate layer of said plurality of layers, and said third interconnect located on a top-most layer of said plurality of layers.
6. An electronic apparatus according to claim 4 , wherein said first interconnect is configured to feed said first differential input to said first set of polysilicon fingers from two opposing directions.
7. An electronic apparatus according to claim 4 , wherein said second interconnect is configured to feed said second differential input to said second set of polysilicon fingers from two opposing directions.
8. An electronic apparatus according to claim 4 , wherein the substrate is selected from the group consisting of silicon, silicon-on-insulator, and a III-IV metal.
9. An electronic apparatus according to claim 4 , further comprising:
a fourth interconnect coupled to said second interconnect and said second set of polysilicon fingers, said fourth interconnect having a fourth lengthwise axis that is perpendicular to said second lengthwise axis.
10. An electronic apparatus according to claim 9 , wherein
the first interconnect and the third interconnect form portions of a first plurality of stacked interconnects that is coupled to said first set of polysilicon fingers, and said third interconnect a top-most stacked interconnect of said first plurality of stacked interconnects, and wherein
the second interconnect and the fourth interconnect form portions of a second plurality of stacked interconnects that is coupled to said second set of polysilicon fingers, and said second interconnect a top-most stacked interconnect of said second plurality of stacked interconnects.
11. An electronic apparatus formed on a substrate, the electronic apparatus comprising:
a first set of polysilicon fingers coupled to the substrate and configured to receive a first differential input signal;
a first interconnect formed of a first metal layer and coupled to said first set of polysilicon fingers and having a first lengthwise axis;
a second set of polysilicon fingers coupled to the substrate and interdigitated with the first set of polysilicon fingers, wherein the second set of polysilicon fingers is configured to receive a second differential input signal;
a second interconnect formed of a second metal layer and coupled to said second set of polysilicon fingers and having a second lengthwise axis, said second lengthwise axis parallel to said first lengthwise axis;
a third interconnect coupled to said first interconnect and said first set of polysilicon fingers, said third interconnect having a third lengthwise axis that is perpendicular to said first lengthwise axis, wherein the third interconnect is formed of a different layer from the second metal layer; and
an air bridge between said third interconnect and said second interconnect.
12. An electronic apparatus according to claim 11 , wherein the first, second, and third interconnects are formed of a plurality of layers, said second interconnect is located on a penultimate layer of said plurality of layers, and said third interconnect located on a top-most layer of said plurality of layers.
13. An electronic apparatus according to claim 11 , further comprising:
a fourth interconnect coupled to said second interconnect and said second set of polysilicon fingers, said fourth interconnect having a fourth lengthwise axis that is perpendicular to said second lengthwise axis, wherein
the first interconnect and the third interconnect form portions of a first plurality of stacked interconnects that is coupled to said first set of polysilicon fingers, and said third interconnect a top-most stacked interconnect of said first plurality of stacked interconnects, and wherein
the second interconnect and the fourth interconnect form portions of a second plurality of stacked interconnects that is coupled to said second set of polysilicon fingers, and said second interconnect a top-most stacked interconnect of said second plurality of stacked interconnects.
14. An electronic apparatus according to claim 13 , wherein said first interconnect and said third interconnect are configured to feed said first differential input to said first set of polysilicon fingers from two opposing directions.
15. An electronic apparatus according to claim 13 , wherein said second interconnect and said fourth interconnect are configured to feed said second differential input to said second set of polysilicon fingers from two opposing directions.
16. An electronic apparatus according to claim 11 , wherein the substrate is selected from the group consisting of silicon, silicon-on-insulator, and a III-IV metal.