IP Library Granted Patent US 7,676,769
Granted Patent B2
US 7,676,769 · App. 11/678,971 · Granted Mar 9, 2010

Adaptive threshold wafer testing device and method thereof

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,676,769
App. No.
11/678,971
Granted
Mar 9, 2010
Kind
B2
Abstract

Techniques for testing a semiconductor wafer are disclosed. One technique includes measuring a parameter for each of the semiconductor dies in a region of the wafer and determining an adaptive threshold for the region based on the measured parameters. The parameter measured for each die in the region is then compared to the adaptive threshold to determine a qualification status for each die. Accordingly, the semiconductor dies of the wafer are qualified based on an adaptive threshold that varies according to the wafer region under test. This allows for detection of dies whose parameters vary significantly from other dies in a region, providing for detection of potentially faulty dies whose parameter measurements otherwise meet a fixed threshold set for the entire wafer, such as a Single Threshold Test Limit (STL) expectation for the wafer.

Claims (47)

1. A method, comprising:

accessing at a computer processor first test data comprising a first plurality of parameter measurement values, each of the first plurality of parameter measurement values associated with a corresponding one of a first subset of semiconductor dies of a wafer comprising a first region and a second region, the first subset associated with the first region, wherein the first plurality of parameter measurements comprise parameter measurements of a first type, the first type selected from the group consisting of: quiescent current supply measurements, clock speed measurements, port input leakage measurements, and transistor threshold voltage measurements;

determining at the computer processor a first parameter threshold for the first subset of semiconductor dies based on the first plurality of parameter measurement values and not based on a second plurality of parameter measurement values associated with the second region, the first parameter threshold comprising a first adaptive threshold associated with the first subset of semiconductor dies;

determining at the computer processor a first qualification status of a first die of the first subset based on a relationship between the first parameter threshold and one of the first plurality of parameter measurement values corresponding to the first die; and

storing at the computer processor a value representative of the first qualification status of the first die.

2. The method of claim 1 , further comprising:

accessing at the computer processor second test data comprising the second plurality of parameter measurement values, each of the second plurality of parameter measurement values associated with a corresponding one of a second subset of semiconductor dies of the wafer;

determining at the computer processor a second parameter threshold for the second subset of semiconductor dies based on the second plurality of parameter measurement values;

determining at the computer processor a second qualification status of a second die of the second subset based on a relationship between the second parameter threshold and one of the second plurality of parameter measurement values corresponding to the first die; and

storing the first qualification status of the second die.

3. The method of claim 2 , wherein determining the first parameter threshold comprises determining the first parameter threshold based on a first calculation process and determining the second parameter threshold comprises determining the first parameter threshold based on the first calculation process.

4. The method of claim 2 , determining the first parameter threshold comprises determining the first parameter threshold with a based on a first calculation process and determining the second parameter threshold comprises determining the first parameter threshold based on a second calculation process, the second calculation process different from the first.

5. The method of claim 2 , wherein the first region includes dies located in disparate areas of the wafer.

6. The method of claim 1 , wherein determining the first parameter threshold comprises determining an average of the first plurality of parameter measurements.

7. The method of claim 6 , wherein determining the first parameter threshold further comprises adjusting the average by an offset.

8. The method of claim 7 , wherein the offset is three standard deviations of the first plurality of parameter measurements.

9. The method of claim 1 , further comprising:

accessing at the computer device second test data comprising a second plurality of parameter measurement values, each of the second plurality of parameter measurements associated with a corresponding one of the first subset of semiconductor dies;

determining at the computer device a second parameter threshold for the first subset of semiconductor dies based on the second plurality of parameter measurement values;

determining at the computer device a second qualification status of the first die based on a relationship between the second parameter threshold and one of the second plurality of parameter measurement values corresponding to the first die; and

storing at the computer device a value representative of the second qualification status of the first die.

10. The method of claim 9 , wherein the first plurality of parameter measurements is associated with a first parameter type the second plurality of parameter measurements are associated with a second parameter type.

11. The method of claim 9 , wherein the first plurality of parameter measurements is associated with a first configuration of the first die, and the second plurality of parameter measurements are associated with a second configuration of the second die.

12. The method of claim 9 , wherein determining a first qualification status of the first die further comprises determining the first qualification status based on a relationship between a predetermined specified threshold associated with the wafer and the one of the first plurality of parameter measurement values corresponding to the first die.

13. A device comprising computer readable media, the computer readable media comprising instructions to manipulate a processor to execute the instruction, the instructions comprising:

instructions to access first test data comprising a first plurality of parameter measurement values, each of the first plurality of parameter measurement values associated with a corresponding one of a first subset of semiconductor dies of a wafer comprising a first region and a second region, the first subset associated with the first region, wherein the first plurality of parameter measurements comprise parameter measurements of a first type, the first type selected from the group consisting of: quiescent current supply measurements, clock speed measurements, port input leakage measurements, and transistor threshold voltage measurements;

instructions to determine a first parameter threshold for the first subset of semiconductor dies based on the first plurality of parameter measurement values and not based on a second plurality of parameter values associated the second region;

instructions to determine a first qualification status of a first die of the first subset based on a relationship between the first parameter threshold and one of the first plurality of parameter measurement values corresponding to the first die; and

instructions to store the first qualification status of the first die.

14. The device of claim 13 , wherein the instructions further comprise:

instructions to access second test data comprising the second plurality of parameter measurement values, each of the second plurality of parameter measurements associated with a corresponding one of a second subset of semiconductor dies of the wafer;

instructions to access a second parameter threshold for the second subset of semiconductor dies based on the second plurality of parameter measurement values;

instructions to determine a second qualification status of a second die of the second subset based on a relationship between the second parameter threshold and one of the second plurality of parameter measurements corresponding to the first die; and

instructions to store the first qualification status of the second die.

15. The device of claim 14 , wherein the first region includes dies located in disparate areas of the wafer.

16. The device of claim 13 , wherein the instructions to determine the first parameter threshold comprise instructions to determine the first parameter threshold based on a first calculation process and determining the second parameter threshold comprises determining the first parameter threshold based on the first calculation process.

17. The device of claim 13 , wherein the instructions to determine the first parameter threshold comprise instructions to determine the first parameter threshold based on a first calculation process and determining the second parameter threshold comprises determining the first parameter threshold based on a second calculation process, the second calculation process different from the first.

18. The device of claim 13 , wherein the instructions further comprise:

instructions to access second test data comprising a second plurality of parameter measurement values, each of the second plurality of parameter measurement values associated with a corresponding one of the first subset of semiconductor dies;

instructions to determine a second parameter threshold for the first subset of semiconductor dies based on the second plurality of parameter measurement values;

instructions to determine a second qualification status of the first die based on a relationship between the second parameter threshold and one of the second plurality of parameter measurement values corresponding to the first die; and

instructions to store a value representing the second qualification status of the first die.

19. A device, comprising:

a first interface module configured to receive first test data comprising a first plurality of parameter measurement values, each of the first plurality of parameter measurement values associated with a corresponding one of a first subset of semiconductor dies of a wafer, wherein the first plurality of parameter measurements comprise parameter measurements of a first type, the first type selected from the group consisting of: quiescent current supply measurements, clock speed measurements, port input leakage measurements, and transistor threshold voltage measurements;

an adaptive threshold configuration module configured to determine a first parameter threshold for the first subset of semiconductor dies;

a qualification module configured to determine a first qualification status of a first die of the first subset based on a relationship between the first parameter threshold and one of the first plurality of parameter measurement values corresponding to the first die; and

a memory configured to store a value representative of the first qualification status.

Assignments (34)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0194 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0640 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0027 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0866 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0120 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Sep 3, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024933/0340 →
SECURITY AGREEMENT Recorded Sep 3, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 024933/0316 →
SECURITY AGREEMENT Recorded Sep 1, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024915/0759 →
SECURITY AGREEMENT Recorded Sep 1, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 024915/0777 →