Method and system for clock skew reduction in clock trees
View Patent ↗A system that includes a clock tree and multiple variable delay components. The system is characterized by including a first set of fuses indicative of identities of variable delay components that belong to a first set of variable delay components, a second set of fuses indicative of delay values of the variable delay components that belong to the first set of variable delay components, and a second set of variable delay components that are set to at least one default delay value. A method for reducing clock skews, the method includes providing a clock tree that includes a set of variable delay components. The method is characterized by selecting a first set of variable delay components in view of timing violations occurring due clock skews, setting delay values of variable delay components that form a first set of variable delay components by programming fuses, and setting delay values of variable delay components that form a second set of variable delay components to at least one default value.
1. A method for reducing clock skews, the method comprises:
providing a clock tree including a plurality of variable delay components, each branch of the clock tree including a single variable delay component; and
setting a corresponding delay value of each variable delay component included at a first set of the variable delay components comprising setting a delay value of a first variable delay component by configuring a first set of fuses to indicate an identity of the first variable delay component, and by configuring a second set of fuses to indicate a delay value of the first variable delay component, and setting a corresponding delay value of each variable delay component included at a second set of the variable delay components to at least one default value, wherein a number of variable delay components included at the first set is less than one half of a number of variable delay components included at the second set.
2. The method according to claim 1 wherein the setting is preceded by selecting the first set of variable delay components.
3. The method according to claim 2 wherein the selecting comprises determining timing violations occurring due to clock skews.
4. The method according to claim 2 wherein the selecting comprises determining timing margins associated with multiple clock paths within the clock tree.
5. The method according to claim 4 wherein the determining of timing margins comprises testing test paths, whereas a delay of a test path is shorter than a delay of an operational path associated with the test path.
6. The method according to claim 5 wherein the testing comprises performing static timing analysis of the test paths.
7. A method for reducing clock skews, the method comprises:
providing a clock tree including a plurality of variable delay components, each branch of the clock tree including a single variable delay component;
selecting a first set of variable delay components of the plurality of variable delay components in view of timing violations occurring due to clock skews;
setting a corresponding delay value of each variable delay component included at the first set comprising setting a delay value of a first variable delay component by configuring a first set of fuses to indicate an identity the first variable delay component, and by configuring a second set of fuses to indicate a delay value of the first variable delay component; and
setting a corresponding delay value of each variable delay component included at a second set of variable delay components of the plurality of variable delay components to at least one default value.
8. The method according to claim 7 wherein selecting comprises determining timing violations occurring due to clock skews.
9. The method according to claim 7 wherein selecting comprises determining timing margins associated with multiple clock paths within the clock tree.
10. The method according to claim 9 wherein determining timing margins comprises testing test paths, and wherein a delay of a test path is shorter than a delay of an operational path associated with the test path.
11. The method according to claim 10 wherein testing comprises performing static timing analysis of the test paths.
12. The method according to claim 7 wherein providing comprises providing variable delay components at locations that define long non-common paths with edges of the clock tree.
13. A system, comprising:
a clock tree including multiple variable delay components including a first set and a second set of variable delay components, each branch of the clock tree including a single variable delay component;
a first set of fuses coupled to the multiple variable delay components to identify variable delay components included at the first set of variable delay components; and
a second set of fuses coupled to the multiple variable delay components to identify a corresponding delay value associated with each variable delay component included at the first set of variable delay components, a corresponding delay value of each variable delay component included at the second set of variable delay components being set to at least one default delay value.
14. The system according to claim 13 further comprising a selection circuit coupled to the first set of fuses, wherein the selection circuit is to send each variable delay component included at the first set of variable delay components a delay value of that variable delay component.
15. The system according to claim 13 wherein a number of variable delay components included at the first set of variable delay components is less than one half of a number of variable delay components included at the second set of variable delay components.
16. The system according to claim 13 further comprising multiple test paths wherein a delay of a test path is shorter than a delay of an operational path associated with the test path.
17. The system according to claim 13 wherein the variable delay components that belong to the first set of variable delay components and to the second set of variable delay components are located at locations that define long non-common paths with edges of the clock tree.
18. The system according to claim 13 wherein a number of variable delay components included at the first set of variable delay components is less than one sixth of a number of variable delay components included at the second set of variable delay.