Transistors with dual layer passivation
View Patent ↗Semiconductor devices are provided with dual passivation layers. A semiconductor layer is formed on a substrate and covered by a first passivation layer (PL- 1 ). PL- 1 and part of the semiconductor layer are etched to form a device mesa. A second passivation layer (PL- 2 ) is formed over PL- 1 and exposed edges of the mesa. Vias are etched through PL- 1 and PL- 2 to the semiconductor layer where source, drain and gate are to be formed. Conductors are applied in the vias for ohmic contacts for the source-drain and a Schottky contact for the gate. Interconnections over the edges of the mesa couple other circuit elements. PL- 1 avoids adverse surface states near the gate and PL- 2 insulates edges of the mesa from overlying interconnections to avoid leakage currents. An opaque alignment mark is desirably formed at the same time as the device to facilitate alignment when using transparent semiconductors.
1. A semiconductor device comprising:
a substrate having a principal surface;
a semiconductor layer on the principal surface of the substrate, wherein the semiconductor layer is substantially optically transparent at a wavelength used for alignment and has an outer surface;
a first dielectric layer on the outer surface;
a device region and an alignment region formed in the first dielectric layer above the principal surface, wherein the device region comprises an upper surface covered by the first dielectric layer with exposed lateral edges where the first dielectric layer and the semiconductor layer have been removed;
an optically opaque region on the alignment region, wherein the optically opaque region is optically opaque at the wavelength used for alignment;
a second dielectric layer over the device region and the optically opaque region on the alignment region, wherein the second dielectric layer is a single and substantially contiguous layer that continuously covers the entire upper surface of the device region and that also completely covers the exposed lateral edges of the device region; and
an alignment pattern formed in the second dielectric layer on the alignment region; and
one or more vias in the dielectric layers on the device region.
2. The device of claim 1 , wherein the semiconductor layer comprises GaN.
3. The device of claim 1 , wherein the optically opaque region comprises silicon.
4. The device of claim 1 , wherein the first dielectric layer comprises Si 3 N 4 , SiO 2 , SiO x N y , AlN, or Al 2 O 3 , or combinations or mixtures thereof.
5. The device of claim 1 , wherein the second dielectric layer comprises Si 3 N 4 , SiO 2 , SiO x N y , AlN, or Al 2 O 3 , or combinations or mixtures thereof.
6. The device of claim 1 , further comprising:
source-drain vias and a gate via formed through the first and second dielectric layers to the upper surface of the semiconductor layer in the device region;
conductors in the vias, which provide ohmic contact to the semiconductor layer in the source-drain vias and a Schottky contact to the semiconductor layer in the gate via; and
at least one conductive interconnect electrically connected to at least one of the source-drain vias, wherein a portion of the at least one conductive interconnect is formed on a portion of the second dielectric layer that covers the exposed lateral edges of the device mesa.
7. The device of claim 1 , wherein
the alignment region is located a pre-determined distance from the device region.
8. The device of claim 1 , wherein the semiconductor layer comprises a III-V compound.
9. The device of claim 1 , wherein the first and second dielectric layers are formed of a same material.
10. The device of claim 1 , wherein the second dielectric layer comprises silicon and nitrogen.
11. The device of claim 1 , wherein the conductors in the vias comprise source-drain contacts comprising aluminum.
12. The method of claim 1 , wherein the conductors in the vias comprise a gate conductor comprising Ni or Pt.