Zero input current-drain comparator with high accuracy trip point above supply voltage
View Patent ↗A comparator circuit ( 300 ) has a first field effect transistor (FET) ( 307 ) with a supply voltage ( 301 ) connection and a diode connected FET ( 303 ) connected in series to form the first circuit leg of the comparator ( 300 ). A second diode connected FET ( 309 ) and a second FET ( 305 ) in series form the second circuit leg. The first FET ( 307 ) and said second FET ( 305 ) are approximately equal sized FETs. Another embodiment is an integrated circuit ( 401 ) with two n-channel FETs. A first diode connected FET ( 303 ) is connected to the first n-channel FET ( 307 ) in series to form the first circuit leg of a comparator ( 300 ) and a second diode connected FET ( 309 ) is connected to a second n-channel FET ( 305 ) in series to form the second circuit leg of the comparator. The two n-channel FETs that form the differential pair are approximately equal in size. The trip point is high with respect to the supply voltage.
1. A circuit comprising a comparator, the comparator comprising:
a first field effect transistor (FET) having a voltage input at a first FET gate terminal, said first FET having a first current terminal to receive a supply voltage;
a first offset voltage circuit connected to a second current terminal of said first FET in series, said first FET and said first offset voltage circuit forming a first circuit leg;
a second offset voltage circuit having a connection for receiving said supply voltage; and
a second FET having a first current terminal coupled to said second offset voltage circuit in series, the second FET and second offset voltage circuit forming a second circuit leg, said second circuit leg connected to said first circuit leg in parallel and forming a parallel circuit, said first FET and said second FET being approximately equal in size and forming a differential pair via said parallel circuit wherein the voltage input at the first FET gate terminal is uncoupled from a gate terminal of the second FET.
2. The circuit of claim 1 , wherein said first offset voltage circuit and said second offset voltage circuit each comprise a component selected from the group of: a diode, a diode connected FET, a diode connected depletion type p-channel MOSFET, and a diode connected bi-polar junction transistor (BJT).
3. The circuit of claim 1 , wherein said comparator has a trip point voltage above said supply voltage.
4. The circuit of claim 1 , further comprising:
a current source circuit connected in series with said first circuit leg and said second circuit leg.
5. The circuit of claim 4 , wherein said current source circuit is comprised of a temperature controlled resistor.
6. The circuit of claim 5 , wherein said temperature controlled resistor is an n-well resistor.
7. The circuit of claim 5 , wherein said current source further comprises:
a depletion type Metal Oxide Semiconductor FET (MOSFET) connected in series with said temperature controlled resistor, said MOSFET having a MOSFET temperature coefficient for canceling out a resistor temperature coefficient of said temperature controlled resistor.
8. The circuit of claim 1 , wherein said first FET and said second FET are depletion type n-channel MOSFETs.
9. The circuit of claim 1 , wherein said second FET includes a reference voltage input at the second FET gate terminal wherein said reference voltage input is different from said supply voltage.
10. The circuit of claim 1 , wherein said circuit is a component circuit of an integrated circuit.
11. An integrated circuit including a comparator, the comparator comprising:
a first FET having an voltage input at a first FET gate terminal, said first FET having a first current terminal to receive a supply voltage wherein the voltage input at the first FET gate terminal is uncoupled from a gate terminal of the second FET;
a first diode connected FET connected to a second current terminal of said first FET in series, said first FET and said first diode-connected FET forming a first circuit leg;
a second diode connected FET having a connection for receiving said supply voltage; and
a second FET having a first current terminal coupled to said second diode connected FET in series, the second FET and second diode connected FET forming a second circuit leg, said second circuit leg connected to said first circuit leg in parallel and forming a parallel circuit, said first FET and said second FET being approximately equal in size and forming a differential pair via said parallel circuit.
12. The integrated circuit of claim 11 , further comprising:
a current source circuit connected in series with said first circuit leg and said second circuit leg.
13. The integrated circuit of claim 12 , wherein said current source circuit comprises a component selected from the group of: a temperature controlled resistor, a diode, a diode connected FET, a diode connected depletion type p-channel MOSFET, and a bi-polar junction transistor (BJT).
14. The circuit of claim 11 , wherein said comparator has a trip point voltage above said supply voltage.
15. The integrated circuit of claim 12 , wherein said current source circuit comprises:
a depletion type MOSFET connected in series with a temperature controlled resistor, said depletion type MOSFET having a temperature coefficient opposite to a resistor temperature coefficient of said temperature controlled resistor, and wherein said temperature controlled resistor is an n-well resistor.
16. The integrated circuit of claim 12 , wherein said first diode connected FET and said second diode connected FET are depletion type p-channel MOSFETs.
17. The integrated circuit of claim 14 , further comprising:
a trimmed precision reference voltage circuit connected to a gate terminal of said second FET for providing a reference voltage thereto.
18. An electronic device comprising the integrated circuit of claim 11 , wherein the electronic device further comprises:
an external connector having an external device identification pin connected to said first FET gate terminal of said first FET.
19. A method of fabricating a comparator circuit on an integrated circuit comprising:
providing a first field effect transistor (FET) having a voltage input at a first FET gate terminal, said first FET having a first current terminal to receive a supply voltage;
providing a first offset voltage circuit connected to a second current terminal of said first FET in series, said first FET and said first offset voltage circuit forming a first circuit leg;
providing a second offset voltage circuit having a connection for said supply voltage; and
providing a second FET having a first current terminal coupled to said second offset voltage circuit in series, the second FET and second offset voltage circuit forming a second circuit leg, said second circuit leg connected to said first circuit leg in parallel and forming a parallel circuit, said first FET and said second FET being approximately equal in size and forming a differential pair via said parallel circuit.
20. The method of claim 19 , wherein said first FET and said second FET are n-channel MOSFETS and wherein said first offset voltage circuit and said second offset voltage circuit are diode connected p-channel MOSFETS.