Flip-flop having logic state retention during a power down mode and method therefor
View Patent ↗A flip-flop includes a master latch, a first inverter, a slave latch, and a first clocked inverter. The master latch has an input for receiving an input signal and an output. The first inverter has an input coupled to the output of the master latch and an output for providing an output of the flip-flop. The slave latch is directly connected to the input of the first inverter. The first clocked inverter has an input directly connected to the slave latch and an output coupled to the master latch.
1. A flip-flop, comprising:
a master latch having an input for receiving an input signal and an output;
a first inverter having an input coupled to the output of the master latch and an output for providing an output of the flip-flop;
a slave latch directly connected to the input of the first inverter, wherein the master latch and the slave latch together function to provide a flip-flop operation during a normal operating mode, and wherein the slave latch functions to retain a logic state of the flip-flop during a power down operating mode; and
a first clocked inverter having an input directly connected to the slave latch and an output coupled to the master latch, wherein the first clocked inverter functions to transfer the logic state to the master latch when operation of the flip-flop returns to the normal operating mode.
2. The flip-flop of claim 1 , wherein the first clocked inverter is enabled in response to a power down signal becoming active.
3. The flip-flop of claim 2 , further comprising a second inverter, wherein the output of the master latch is coupled to the input of the first inverter through the second inverter.
4. The flip-flop of claim 3 , wherein a power down period comprises a continuous time duration between the power down signal becoming active and the power down signal becoming inactive and wherein, during a portion of the power down period, power is removed from the master latch and the first inverter and the slave latch remains powered.
5. The flip-flop of claim 4 , further comprising a first transmission gate, wherein the output of the master latch is coupled to the input of the first inverter through the first transmission gate.
6. The flip-flop of claim 5 , wherein the slave latch comprises:
a third inverter having an input having an input directly connected to the input of the first inverter and an output coupled to the input of the first clocked inverter; and
a second clocked inverter having an input coupled to the output of the third inverter and an output coupled to the input of the third inverter.
7. The flip-flop of claim 6 , wherein the master latch comprises:
a fourth inverter having an input for receiving the input signal and an output coupled to the input of the first inverter; and
a third clocked inverter having an input coupled to the output of the fourth inverter and an output coupled to the input of the fourth inverter.
8. The flip-flop of claim 7 , further comprising a fourth clocked inverter having an input for receiving a data signal and an output for providing the input signal.
9. The flip-flop of claim 8 , further comprising a first clock circuit that has inputs that receive a clock signal and the power down signal and provides a first clocking signal to the second clocked inverter.
10. The flip-flop of claim 9 , further comprising a second clock circuit that has inputs that receive the clock signal and the power down signal and an output that provides a second clocking signal to the fourth clocked inverter.
11. A method, comprising:
during a normal mode of operation of a flip-flop comprising a master latch and a slave latch:
latching an input signal in the master latch on a first edge of a clock signal;
selectively coupling the input signal to an output circuit; and
latching the input signal in the slave latch that is directly connected to the output circuit on a second edge of the clock signal;
in response to entering a power down period:
disabling the master latch; and
coupling the slave latch to the master latch and transferring a logic state of the master latch to the slave latch;
during a portion of the power down period; removing power from the master latch and the output circuit while retaining power to the slave latch; and
in response to a termination of the power down period, which occurs after power has returned to the master latch, transferring the logic state of the slave latch back to the master latch, and decoupling the slave latch from the master latch.
12. The method of claim 11 , wherein the step of coupling the slave latch to the master latch is performed by a clocked inverter that is enabled by a power down signal.
13. The method of claim 12 , further comprising removing power from the clocked inverter during the portion of power down period.
14. The method of claim 13 , further comprising restoring power to the clocked inverter after termination of the portion of the power down period and before termination of the power down period.
15. The method of claim 11 , further comprising providing an output signal from the output circuit representative of the input signal latched in the slave latch after termination of the portion of the power down period and before termination of the power down period.
16. A flip-flop, comprising:
a master latch having an input for receiving an input signal and output;
an output circuit coupled to the master latch for providing an output signal of the flip-flop;
a slave latch directly connected to the output circuit for storing a logic state received by the output circuit; and
a first clocked inverter having an input directly connected to the slave latch and an output coupled to the master latch for providing the logic state stored in the slave latch to the master latch at a time prior to termination of a power down period;
wherein the slave latch provides the logic state stored in the slave latch to the output circuit at the time prior to termination of a power down period, and
wherein the output circuit provides the output signal responsive to the slave latch providing the logic state stored in the slave latch, and wherein during a portion of the power down period, power is removed from the master latch and the output circuit and the slave latch is powered.
17. The flip-flop of claim 16 , wherein the first clocked inverter is clocked by a power down signal that defines a beginning and an end of the power down period.
18. The flip-flop of claim 16 , wherein:
the master latch comprises a first pair of cross coupled inverters in which one of the pair is clocked;
the slave latch comprises a second pair of cross coupled inverters in which one of the pair is clocked; and
the output circuit is coupled to the master latch through a first inverter and a transmission gate.
19. The flip-flop of claim 18 , further comprising a second clocked inverter for receiving a data signal and providing the input signal wherein the second clocked inverter, the master latch, the slave latch, and the transmission gate are clocked by signals derived from a clock signal and a power down signal.