Method of manufacturing a passive integrated matching network for power amplifiers
An impedance matching network is integrated on a first die and coupled to a second die, with the first and second dies mounted on a conductive back plate. The impedance matching network comprises a first inductor bridging between the first and second dies, a second inductor coupled to the first inductor and disposed on the first die, and a metal-insulator-metal (MIM) capacitor disposed on the first die. The MIM capacitor has a first metal layer coupled to the second inductor, and a second metal layer grounded to the conductive back plate. A method for manufacturing the integrated impedance matching network comprises the steps of forming an inductor on a die, forming a capacitor on the die, coupling the capacitor to the inductor, coupling the die bottom surface and the capacitor to a conductive plate, and coupling the inductor to another inductor that bridges between the die and another die.
1. A method of manufacturing an integrated impedance matching network, the method comprising the steps of:
forming a first inductor on a first die having top and bottom surfaces;
forming a capacitor first metal layer on the first die top surface;
forming an insulator layer on the capacitor first metal layer;
forming a capacitor second metal layer on the insulator layer;
coupling the capacitor second metal layer to the first inductor;
mounting the first die bottom surface to a conductive plate;
coupling the capacitor first metal layer to the conductive plate; and
coupling the first inductor to a second inductor that bridges between the first die and a second die that is mounted on the conductive plate.
2. The method according to claim 1 , wherein the first die comprises an insulating or semi-insulating substrate.
3. The method according to claim 2 , wherein the first die comprises GaAs.
4. The method according to claim 1 , wherein the first die is between about 75 and about 200 μm in thickness.
5. The method according to claim 1 , wherein the second inductor comprises a plurality of bond wires, and the first inductor comprises a plurality of metal strips.
6. The method according to claim 5 , wherein each of the metal strips is more than 8 μm in thickness, and more than 40 μm in width.
7. The method according to claim 5 , wherein each of the bond wires is between about 10 mils and about 30 mils in height.
8. The method according to claim 1 , wherein the second die is an LDMOS die.
9. The method according to claim 1 , wherein the second die is a III-V compound semiconductor die.
10. The method according to claim 1 , wherein the second die comprises a power amplification circuit.
11. The method according to claim 1 , wherein the step of coupling the capacitor first metal layer to the conductive plate comprises the steps of:
forming a via hole through the first die before mounting the first die bottom surface; and
filling the via hole with an interconnect metal.
12. The method according to claim 1 , wherein the first inductor, and the capacitor first and second metal layers are formed from the same materials.
13. The method according to claim 1 , wherein the step of coupling the capacitor second metal layer to the first inductor includes forming a third metal layer that connects the capacitor second metal layer to the first inductor.
14. The method according to claim 13 , wherein the first inductor, the capacitor first and second metal layers, and the third metal layer, are all formed from the same materials.
15. The method according to claim 1 , wherein the integrated impedance matching network is part of a power amplifier for a base station that amplifies and transmits remote signals.
16. The method according to claim 1 , wherein the step of forming the first inductor is performed while performing one or more of the steps of forming the capacitor first and second metal layers and the step of coupling the capacitor second metal layer to the first inductor.
17. A method of manufacturing an integrated impedance matching network, the method comprising the steps of:
forming a first inductor on a first die having top and bottom surfaces;
forming a first capacitor layer from a first metal on the first die top surface while forming the first inductor using the first metal;
forming an insulator layer on the capacitor first metal layer;
forming a second capacitor layer from a second metal on the insulator layer while continuing to form the first inductor using the second metal;
coupling the capacitor second metal layer to the first inductor;
mounting the first die bottom surface to a conductive plate;
coupling the capacitor first metal layer to the conductive plate; and
coupling the first inductor to a second inductor that bridges between the first die and a second die that is mounted on the conductive plate.
18. The method according to claim 17 , wherein the step of coupling the capacitor second metal layer to the first inductor includes forming a layer from a third metal that connects the capacitor second metal layer to the first inductor, and that further forms the first inductor.
19. The method according to claim 17 , wherein the step of coupling the capacitor first metal layer to the conductive plate comprises the steps of:
forming a via hole through the first die before mounting the first die bottom surface; and
filling the via hole with an interconnect metal.
20. The method according to claim 17 , wherein the second inductor comprises a plurality of bond wires, and the first inductor comprises a plurality of metal strips.