System and method for reducing power consumption of a transistor-based circuit having multiple operational modes characterized by different power consumption level
View Patent ↗A method for reducing power consumption, and a system having power reduction capabilities, the method includes: storing, at a first circuit, data representative of a state of a second circuit, entering a low power mode, exiting low power mode, providing a default data value to the second circuit after exiting from the low power mode, and selectively providing data from the first circuit to the second circuit in response to the value of data and to a characteristic of a third circuit coupled to the first and second circuits.
1. A method for reducing power consumption, the method comprises:
storing, at a first circuit, data representative of a state of a second circuit, and entering a low power mode of the first circuit and the second circuit;
providing a default data value to the second circuit after exiting the first and the second circuit from the low power mode, and selectively providing data from the first circuit to the second circuit in response to a value of the data representative of the state of the second circuit and to a characteristic of a third circuit coupled to the first and second circuits.
2. The method according to claim 1 wherein the characteristic reflects a capability of the third circuit to provide the data to the first circuit.
3. The method according to claim 1 wherein the characteristic reflects a distortion introduced by the third circuit.
4. The method according to claim 1 wherein the default data value is in response to the characteristic of the third circuit.
5. The method according to claim 4 wherein the default data value is in responsive to a data value that can be better provided by the third circuit.
6. The method according to claim 4 wherein the default data value differs from the value of the data from the first circuit that can be better written by the third circuit.
7. The method according to claim 1 wherein the third circuit comprises an NMOS transistor and whereas the default value is “1”.
8. The method according to claim 1 wherein entering the low power mode comprises shutting down the third circuit.
9. The method of claim 1 wherein the providing comprises providing the data from the first circuit via the third circuit to the second circuit.
10. The method according to claim 1 further comprising pre-charging the first circuit to a pre-charge default value.
11. The method according to claim 10 wherein the pre-charge default value is responsive to the characteristic of the third circuit.
12. The method according to claim 10 wherein the characteristic of the third circuit reflects a distortion introduced by the third circuit.
13. A method for reducing power consumption, the method comprises:
storing at a first circuit data representative of a state of a second circuit;
entering a low power mode of the first circuit and the second circuit;
exiting a low power mode of the first circuit and the second circuit, characterized by providing a default data value to the second circuit if the data representative of the state of the second circuit has a first value; and
providing data from the first circuit to the second circuit if the data representative of the state of the second circuit has another value;
wherein the first circuit comprises a latch that is powered when the first circuit is in the low power mode; wherein the second circuit comprises a transfer gate, an AND gate and a pair of inverters that are coupled to the AND gate; wherein a third circuit comprises a transistor that is coupled between the latch and between a first node; and wherein the first node is coupled to the transfer gate to an inverter of the pair of inverters.
14. A system having power reduction capabilities, the system comprises:
a third circuit coupled between a first circuit and a second circuit; wherein the first circuit is adapted to store data representative of a state of the second circuit, wherein the first circuit is activated during a low power mode while the second circuit is deactivated during the low power mode;
the second circuit that is adapted to enter a default state after exiting the low power mode; and
wherein the third circuit selectively provides data from the first circuit to the second circuit in response to a value of the data and to a characteristic of the third circuit.
15. The system of claim 14 wherein the second circuit enters the default state in response to a signal indicating an end of the low power mode.
16. The system according to claim 14 wherein the characteristic of the third circuit reflects a capability of the third circuit to provide the data to the first circuit.
17. The system according to claim 14 wherein the characteristic of the third circuit reflects a distortion introduced by the third circuit.
18. The system according to claim 14 wherein the default state is responsive to the characteristic of the third circuit.
19. The system according to claim 14 wherein the default state is determined in response to a data value that can be better provided by the third circuit.
20. The system according to claim 14 wherein the third circuit is shut down during a low power mode.
21. The system according to claim 14 wherein the first circuit comprises a pre-charge circuit for pre-charging the first circuit to a pre-charge default value.
22. The system according to claim 21 wherein the pre-charge default value is responsive to a characteristic of the third circuit.
23. The system according to claim 21 wherein the characteristic of the third circuit reflects a distortion introduced by the third circuit.
24. The system according to claim 14 wherein the first circuit comprises a latch that is powered when in the low power mode; wherein the second circuit comprises a transfer gate an AND gate and a pair of inverters that are coupled to the AND gate; wherein the third circuit comprises a transistor that is coupled between the latch and between a first node; and wherein the first node is coupled to the transfer gate and to an inverter out of the pair of inverters.
25. The method according to claim 1 wherein the first circuit comprises a latch that is powered when in the low power mode; wherein the second circuit comprises a transfer gate, an AND gate and a pair of inverters that are coupled to the AND gate; wherein the third circuit comprises a transistor that is coupled between the latch and between a first node; and wherein the first node is coupled to the transfer gate and to an inverter out of the pair of inverters.