Granted Patent B2

US 7,723,224 · App. 11/453,763 · Granted May 25, 2010

Abstract

Claims (38)

1. A method for forming a microelectronic assembly comprising:

forming a conductor on a first side of a first substrate having a microelectronic device formed over a second side thereof, the conductor being electrically connected to the microelectronic device and comprising a solderable material;

forming a contact structure over the first side of the first substrate, the contact structure being electrically connected to the conductor and comprising a solderable barrier metal, wherein the barrier metal comprises at least one of nickel, chromium-copper, and palladium;

forming a non-solderable layer over the contact structure and at least a portion of the first substrate and the conductor, wherein the non-solderable layer is a passivation layer and comprises silicon nitride;

removing a portion of the non-solderable layer to expose a portion of the contact structure;

forming a solderable layer on the exposed portion of the contact structure; and

interconnecting the contact structure and a second substrate with solder, wherein the solder contacts the exposed portion of the contact structure.

2. The method of claim 1 , wherein the conductor and the solderable layer each comprise at least one of gold, tin, and copper and the solder comprises a lead-free, tin based solder material.

3. The method of claim 1 , wherein the first substrate is a semiconductor substrate and comprises gallium arsenide, and wherein the solderable barrier metal is selected from the group consisting of nickel, chromium-copper, copper, and palladium.

4. The method of claim 1 , further comprising:

mounting the first substrate to a support substrate with an adhesive having a softening temperature of less than 160° C. before the forming of the conductor;

thinning the first substrate from the first side thereof; and

demounting the first substrate from the support substrate after the forming of the contact structure.

5. A method for forming a microelectronic assembly comprising:

forming a conductor over a semiconductor substrate having an integrated circuit formed over a front side thereof, the conductor being electrically connected to the integrated circuit and comprising a first solderable material;

forming a contact structure over a back side of the semiconductor substrate, the contact structure being electrically connected to the conductor and consisting of a solderable barrier metal;

forming a passivation layer over the contact structure and at least a portion of the conductor;

removing a portion of the passivation layer to expose a portion of the contact structure;

forming a solderable layer over the exposed portion of the contact structure, the solderable layer comprising a second solderable material; and

attaching the semiconductor substrate to a package substrate using solder, the solder interconnecting the contact structure and the package substrate,

wherein the first and second solderable materials each comprise at least one of gold, tin, and copper, and the solderable barrier metal is selected from the group consisting of nickel, chromium-copper, copper, and palladium.

6. The method of claim 5 , wherein the conductor is formed over the back side of the semiconductor substrate.

7. The method of claim 6 , wherein the attaching of the semiconductor substrate to the package substrate comprises heating the solder, said heating causing intermetallic compound formation between the solder and the solderable layer.

8. The method of claim 7 , wherein the semiconductor substrate comprises gallium arsenide has a first thickness and further comprising:

mounting the semiconductor substrate to a support substrate having a first thickness with an adhesive having a softening temperature of below 160° C., the support substrate being adjacent to the front side of the semiconductor substrate and comprising at least one of sapphire and quartz;

thinning the semiconductor substrate from the first thickness to a second thickness, the second thickness being less than 200 microns; and

demounting the semiconductor substrate from the support substrate after the forming of the solderable layer and before the attaching of the semiconductor substrate to the package substrate.

9. A microelectronic assembly comprising:

a first substrate having a microelectronic device formed over a front side thereof;

a conductor formed over a back side of the first substrate, the conductor being electrically connected to the microelectronic device;

a contact structure formed over the conductor, the contact structure having a plurality of lateral sides and a top side and being electrically connected to the conductor, the top side of the contact structure having first and second portions, the contact formation consisting of a solderable barrier metal;

a non-solderable layer formed over the conductor, the lateral sides of the contact structure, and the first portion of the contact structure;

a solder formation bonded to the second portion of the top side of the contact structure; and

a second substrate bonded to the solder formation,

wherein the conductor comprises at least one of gold, tin, and copper and the solderable barrier metal is selected from the group consisting of nickel, chromium-copper, copper, and palladium.

10. The microelectronic assembly of claim 9 , wherein the first substrate is a semiconductor substrate and the microelectronic device comprises at least one transistor.

11. The microelectronic assembly of claim 10 , wherein the non-solderable layer comprises silicon nitride.

12. The microelectronic assembly of claim 11 , wherein the semiconductor substrate comprises gallium arsenide and the second substrate is a package substrate.

Assignments (20)