IP Library Granted Patent US 7,102,359
Granted Patent B2
US 7,102,359 · App. 11/247,480 · Granted Sep 5, 2006

Integrated fault detector circuit

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Quick Facts
Patent No.
US 7,102,359
App. No.
11/247,480
Granted
Sep 5, 2006
Kind
B2
Abstract

According to one embodiment, an integrated fault detector circuit is used to detect one or more of the open circuit and short circuit of a load connected to an integrated circuit power MOSFET driver by directly detecting the level of current flowing in a floating current source.

Claims (36)

1. A fault detector circuit comprising:

a high current switch having a first and second terminals;

a floating current source;

a first current mirror configuration, the first current mirror configuration and the floating current source being coupled in series between the first and second terminals of the high current switch;

a second current mirror configuration coupled to the first current mirror configuration, wherein a current flowing through the floating current source is mirrored by the first current mirror configuration to the second current mirror configuration, further wherein the current contains information concerning one of a normal load, an open load, or a shorted load condition on the high current switch; and

a Schmitt trigger having an input and an output, wherein the second current mirror configuration is coupled to the input of the Schmitt trigger and wherein the Schmitt trigger output is representative of one of a faulted state or an un-faulted state, as a function of one of the normal load condition, the open load condition, or the shorted load condition on the high current switch.

2. The circuit of claim 1 , wherein the high current switch comprises a high current switch transistor.

3. The circuit of claim 2 , wherein the first terminal corresponds to a drain terminal and the second terminal corresponds to a source terminal.

4. The circuit of claim 2 , further wherein the high current switch transistor comprises a high current MOSFET transistor.

5. The circuit of claim 1 , wherein the first mirror configuration is of a first polarity, and wherein the second mirror configuration is of a second polarity, the second polarity being opposite to the first polarity.

6. The circuit of claim 1 , wherein the Schmitt trigger is configured for non-inverting operation.

7. The circuit of claim 1 , further comprising a constant current source transistor coupled to an input of the Schmitt trigger.

8. The circuit of claim 7 , further wherein a drain of the constant current source transistor is coupled to the input of the Schmitt trigger, said circuit further comprising:

a zener diode coupled to an input of the Schmitt trigger, wherein the zener diode limits a maximum voltage at the drain of the constant current source transistor.

9. The circuit of claim 1 , further comprising a load, wherein the load is coupled to the circuit in one of (i) a low-side drive configuration or (ii) a high-side drive configuration.

10. The circuit of claim 9 , wherein for the low-side drive configuration, the load is coupled between the first terminal of the high current switch and a first voltage and wherein the second terminal of the high current switch is coupled to a second voltage.

11. The circuit of claim 10 , wherein the first voltage is greater than the second voltage.

12. The circuit of claim 9 , wherein for the high-side drive configuration, the load is coupled between the second terminal of the high current switch and a second voltage, wherein the first terminal of the high current switch is coupled to the first voltage.

13. The circuit of claim 12 , wherein the first voltage is greater than the second voltage.

14. A fault detector circuit comprising:

a high current switch transistor having a first and second terminals, wherein the first terminal corresponds to a drain terminal and the second terminal corresponds to a source terminal;

a floating current source;

a first current mirror configuration, the first current mirror configuration and the floating current source being coupled in series between the first and second terminals of the high current switch;

a second current mirror configuration coupled to the first current mirror configuration, wherein the first mirror configuration is of a first polarity, and wherein the second mirror configuration is of a second polarity, the second polarity being opposite to the first polarity, and further wherein a current flowing through the floating current source is mirrored by the first current mirror configuration to the second current mirror configuration, the current containing information concerning one of a normal load, an open load, or a shorted load condition on the high current switch; and

a Schmitt trigger having an input and an output, wherein the second current mirror configuration is coupled to the input of the Schmitt trigger and wherein the Schmitt trigger output is representative of one of a faulted state or an un-faulted state, as a function of one of the normal load condition, the open load condition, or the shorted load condition on the high current switch.

15. The circuit of claim 14 , further comprising a load, wherein the load is coupled to the circuit in one of (i) a low-side drive configuration or (ii) a high-side drive configuration.

16. The circuit of claim 15 , wherein for the low-side drive configuration, the load is coupled between the first terminal of the high current switch and a first voltage and wherein the second terminal of the high current switch is coupled to a second voltage, and further wherein for the high-side drive configuration, the load is coupled between the second terminal of the high current switch and a second voltage, wherein the first terminal of the high current switch is coupled to the first voltage.

17. The circuit of claim 16 , still further wherein the first voltage is greater than the second voltage.

18. A fault detection method comprising:

providing a high current switch having a first and second terminals;

coupling a floating current source and a a first current mirror configuration in series between the first and second terminals of the high current switch;

coupling a second current mirror configuration to the first current mirror configuration, wherein a current flowing through the floating current source is mirrored by the first current mirror configuration to the second current mirror configuration, further wherein the current contains information concerning one of a normal load, an open load, or a shorted load condition on the high current switch; and

coupling a Schmitt trigger to the second current mirror configuration, wherein the second current mirror configuration is coupled to the input of the Schmitt trigger and wherein the Schmitt trigger output is representative of one of a faulted state or an un-faulted state, as a function of one of the normal load condition, the open load condition, or the shorted load condition on the high current switch.

19. The method of claim 18 , further comprising:

coupling a load to the high current switch in one of (i) a low-side drive configuration or (ii) a high-side drive configuration.

20. The method of claim 19 , wherein for the low-side drive configuration, the load is coupled between the first terminal of the high current switch and a first voltage and wherein the second terminal of the high current switch is coupled to a second voltage, and further wherein for the high-side drive configuration, the load is coupled between the second terminal of the high current switch and a second voltage, wherein the first terminal of the high current switch is coupled to the first voltage, still further wherein the first voltage is greater than the second voltage.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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