Latch device having low-power data retention
View Patent ↗A latch of an integrated circuit is able to retain data at the latch when the integrated circuit is in a low-power mode. The latch retains data at a retention stage in response to assertion of an isolation signal. In response to a reference voltage supplied to the latch being restored to a normal operating voltage, indicating that the integrated circuit has transitioned from the low-power mode to a normal mode, a data restoration circuit provides the retained data at the output of the latch prior to negation of the isolation signal. This reduces the likelihood that a delay in negation of the isolation signal will result in the latch output providing incorrect data, thereby reducing the likelihood of the latch output causing errors in downstream elements of the integrated circuit.
1. A device, comprising:
a storage circuit comprising:
a data input;
a first control input;
a first voltage reference input coupled to a first voltage reference, the storage circuit configured to store first data when the first voltage reference is at a first level;
an output configured to provide the first data based on a signal at the first control input;
a retention circuit configured to store the first data when the first voltage reference is at a second level whose magnitude is lower than the magnitude of the first level, the retention circuit comprising:
a data input coupled to the output of the storage circuit;
a second control input configured to receive a first isolation signal, the retention circuit configured to store the first data in response to assertion of the isolation signal;
an output to provide the first data; and
a restoration circuit, comprising:
a data input coupled to the output of the retention circuit;
a third control input configured to receive the first isolation signal; and
an output coupled to the output of the storage circuit, the restoration circuit configured to couple the data input of the restoration circuit to the output of the storage circuit when the isolation signal is asserted.
2. The device of claim 1 , wherein the restoration circuit further comprises:
a second voltage reference input;
an inverter comprising an input coupled to the data input of the restoration circuit, an output, and a third voltage input coupled to the second voltage reference input; and
a pass gate comprising a first terminal coupled to the output of the inverter, a second terminal coupled to the output of the restoration circuit, and a control terminal coupled to the third control input.
3. The device of claim 1 , wherein the restoration circuit further comprises:
a second voltage reference input;
a fourth control input configured to receive a second isolation signal;
a first transistor comprising a first current electrode coupled to the second voltage reference input, a second current electrode, and a control electrode coupled to the data input of the restoration circuit;
a second transistor comprising a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to the output of the restoration circuit, and a control electrode coupled to the third control input;
a third transistor comprising a first current electrode coupled to the output of the restoration circuit, a second current electrode, and a control electrode coupled to the fourth control input; and
a fourth transistor comprising a first current electrode coupled to the second current electrode of the third transistor, a second current electrode coupled to a third voltage reference, and a control electrode coupled to the data input of the restoration circuit.
4. The device of claim 1 , wherein the storage circuit comprises a master stage of a master-slave flip-flop.
5. The device of claim 4 , wherein the retention circuit comprises a slave stage of the master-slave flip-flop.
6. The device of claim 1 , wherein the retention circuit further comprises a third voltage reference input coupled to a second voltage reference.
7. The device of claim 6 , wherein the second voltage reference remains at a level sufficient for the retention circuit to store the first data when the first voltage reference is in a low-power mode.
8. The device of claim 1 , wherein the retention circuit comprises:
a first pass gate comprising a first terminal coupled to the input of the retention circuit, a second terminal, and a control terminal coupled to the second control input;
a second pass gate comprising a first terminal coupled to the second terminal of the first pass gate, a second terminal, and a control terminal coupled to the first control input;
a third pass gate comprising a first terminal coupled to the second terminal of the first pass gate, a second terminal coupled to the second terminal of the second pass gate, and a control terminal coupled to the second control input;
a first inverter comprising an input coupled to the second terminal of the first pass gate and an output coupled to the output of the retention circuit;
a second inverter comprising an input coupled to the output of the first inverter and an output coupled to the second terminal of the third pass gate.
9. The device of claim 1 , wherein the storage circuit comprises:
a master stage comprising an input coupled to the data input, a fourth control input coupled to the first control input, and an output, the master stage configured to store data at the data input in response to assertion of a signal at the fourth control input; and
a slave stage comprising an input coupled to the output of the master stage, a fifth control input coupled to the first control input, and an output coupled to the input of the retention circuit, the slave stage configured to store data at the input of the slave stage in response to negation of a signal at the fifth control input.
10. The device of claim 1 , wherein the retention circuit comprises:
a pass gate comprising a first terminal coupled to the data input of the retention circuit, a second terminal, and a control terminal coupled to the second control input;
a first inverter comprising an input coupled to the data input of the retention circuit and an output coupled to the output of the retention circuit; and
a second inverter comprising an input coupled to the output of the retention circuit and an output coupled to the second terminal of the pass gate.
11. The device of claim 1 , wherein the storage circuit comprises:
a first inverter comprising an input coupled to the data input and an output;
a first pass gate comprising a first terminal coupled to the output of the first inverter, a second terminal, and a control terminal coupled to the first control input;
a second inverter comprising an input coupled to the second terminal of the first pass gate and an output;
a third inverter comprising an input coupled to the output of the second inverter and an output; and
a second pass gate comprising a first terminal coupled to the output of the third inverter, a second terminal coupled to the input of the second inverter, and a control terminal coupled to the first control input.
12. The device of claim 11 , wherein the storage circuit further comprises:
a fourth inverter comprising an input coupled to the output of the second inverter and an output; and
a third pass gate comprising a first terminal coupled to the output of the fourth inverter, a second terminal coupled to the output of the device, and a control terminal coupled to the first control input.
13. The device of claim 12 , wherein the storage circuit further comprises a fourth pass gate comprising a first terminal coupled to the second terminal of the third pass gate, a second terminal, and a control terminal coupled to the second control input.
14. The device of claim 13 , wherein the retention circuit further comprises:
a fifth pass gate comprising a first terminal coupled to the second terminal of the fourth pass gate, a second terminal, and a control terminal coupled to the first control input;
a sixth pass gate comprising a first terminal coupled to the second terminal of the fourth pass gate, a second terminal coupled to the second terminal of the fifth pass gate, and a control terminal coupled to the second control input;
a fifth inverter comprising an input coupled to the second terminal of the fourth pass gate and an output; and
a sixth inverter comprising an input coupled to the output of the fifth inverter and an output coupled to the second terminal of the fifth pass gate.
15. The device of claim 13 , wherein the storage circuit further comprises:
a fifth pass gate comprising a first terminal coupled to the second terminal of the fourth pass gate, a second terminal coupled to the data input of the retention circuit, and a control terminal coupled to the first control input;
a fifth inverter comprising an input coupled to the first terminal of the fourth pass gate and an output; and
a sixth inverter comprising an input coupled to the output of the fifth inverter and an output coupled to the data input of the retention circuit.
16. A method, comprising:
receiving a first voltage at a reference voltage input of a latch at a first time;
receiving an asserted isolation signal at the first time;
storing data at a first stage of the latch at the first time in response to the asserted isolation signal;
receiving a second voltage at the reference voltage input at a second time, the second time after the first time;
receiving the first voltage at the reference voltage input at a third time, the third time after the second;
providing the data stored at the first stage of the latch from a restoration stage of the latch to an output of the latch in response to receiving the first voltage at the third time;
de-asserting the isolation signal at a fourth time, the fourth time after the third time, the output of latch maintaining a state in response to the de-asserted isolation signal.
17. The method of claim 16 , wherein the first stage of the latch is a slave stage of a master-slave flip-flop.
18. The method of claim 16 , wherein the second voltage is smaller in magnitude than the first voltage.
19. A method, comprising:
storing data at a first stage of a latch of an integrated circuit when the integrated circuit is in a first power mode;
providing the data stored at the first stage via a first signal path to an output of the latch when the integrated circuit is in an active mode;
maintaining the data stored at the first stage of the latch when the integrated circuit is in a second power mode; and
providing the data maintained at the latch to the output of the latch via a second signal path not including the first stage of the latch in response to a signal indicating the integrated circuit is in the second power mode.
20. The method of claim 19 , wherein the second power mode is a low power mode.