Granted Patent B2

US 7,262,615 · App. 11/263,089 · Granted Aug 28, 2007

Abstract

Claims (26)

1. A method for testing a semiconductor structure having a set of top-side connections and having a set of bottom-side connections, the method comprising:

providing a device socket having an interconnecting side for connecting the set of top-side connections and the set of bottom-side connections to a tester;

providing a device hood for connecting each top-side connection of the set of top-side connections to a corresponding interconnect of a plurality of interconnects in the device hood, and for connecting each interconnect to a corresponding top-side connection, wherein the plurality of interconnects in the device hood connects the set of top-side connections to the device socket, and wherein the plurality of interconnects are routed through the device hood and through the device socket to the interconnecting side of the device socket, such that both the set of top-side connections and the set of bottom-side connections are accessible in a single plane parallel to the interconnecting side of the device socket; and

testing the semiconductor structure using the tester.

2. The method of claim 1 , wherein the set of bottom-side connections comprises at least one of a set of solder cladding, a set of solder balls, a land grid array, a set of pads, and a set of bumps, and the set of top-side connections comprises at least one of a set of solder cladding, a set of solder balls, a land grid array, a set of pads, and a set of bumps.

3. The method of claim 1 , wherein the device hood further comprises a plurality of device hood pins, wherein each one of the plurality of device hood pins is connected to corresponding interconnect of the plurality of interconnects in the device hood.

4. The method of claim 3 , wherein the plurality of device hood pins are spring-loaded pins.

5. The method of claim 1 , wherein the plurality of interconnects in the device hood comprise at least one of a ribbon-cable and a set of wires.

6. The method of claim 1 , wherein the device socket is connected via a load board to the tester.

7. The method of claim 1 , wherein the device socket comprises at least one of a load board and a top surface of the tester.

8. The method of claim 1 , wherein the semiconductor structure comprises at least one integrated circuit, wherein at least a portion of the set of top-side connections is electrically coupled to the at least one integrated circuit.

9. The method of claim 8 , wherein the at least one integrated circuit comprises a plurality of integrated circuits.

10. The method of claim 9 , wherein each of the plurality of integrated circuits is packaged.

11. The method of claim 1 , wherein the device socket and the device hood are pivotally joined.

12. The method of claim 1 , wherein testing the at least one integrated circuit using the integrated circuit tester further comprises simultaneously testing both the set of top-side connections and the set of bottom-side connections.

13. The method of claim 12 , further comprising providing the set of top-side connections and the set of bottom-side connections in a single plane to at least one of a load board and the tester.

14. A method for testing an array of semiconductor structures, each semiconductor structure of the array of semiconductor structures having a set of top-side connections and having a set of bottom-side connections, the method comprising:

providing a device socket having an interconnecting side for connecting the set of top-side connections and the set of bottom-side connections of at least one semiconductor structure of the array of semiconductor structures to a tester;

providing a device hood for connecting each top-side connection of the set of top-side connections to an interconnect of a plurality of interconnects in the device hood, and for connecting each interconnect to a top-side connection wherein the plurality of interconnects in the device hood connects the set of top-side connections of the at least one semiconductor structure of the array of semiconductor structures to the device socket, and wherein the plurality of interconnects are routed through the device hood and through the device socket to the interconnecting side of the device socket, such that both the set of top-side connections and the set of bottom-side connections are accessible in a single plane parallel to the interconnecting side of the device socket; and

testing the at least one semiconductor structure of the array of semiconductor structures using the tester.

15. The method of claim 14 , wherein the set of bottom-side connections comprises at least one of a set of solder cladding, a set of solder balls, a land grid array, a set of pads, and a set of bumps.

16. The method of claim 14 , wherein the device hood further comprises a plurality of device hood pins, wherein each one of the plurality of device hood pins is connected to corresponding interconnect the plurality of interconnects in the device hood.

17. The method of claim 14 , wherein each semiconductor structure of the array of semiconductor structures comprises at least one integrated circuit electrically coupled to at least a portion of the set of top-side connections of the each semiconductor structure.

18. The method of claim 14 , wherein the plurality of interconnects in the device hood comprise at least one of a ribbon-cable and a set of wires.

19. The method of claim 14 , wherein the device socket is connected via a load board to the tester.

20. The method of claim 14 , wherein the device socket is at least one of a load board and a top surface of the tester.

Assignments (23)