IP Library Granted Patent US 7,220,632
Granted Patent B2
US 7,220,632 · App. 11/065,324 · Granted May 22, 2007

Method of forming a semiconductor device and an optical device and structure thereof

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Quick Facts
Patent No.
US 7,220,632
App. No.
11/065,324
Granted
May 22, 2007
Kind
B2
Abstract

An integration process where a first semiconductor protective layer and a second semiconductor protective layer are formed to protect the first and second semiconductor materials, respectfully, during processing to form an optical device, such as a photodetector, and a transistor on the same semiconductor. The first semiconductor protective layer protects the semiconductor substrate during formation of the second semiconductor layer, and the second semiconductor layer protects the second semiconductor material during subsequent processing of the first semiconductor. In one embodiment, the first semiconductor includes silicon and the second semiconductor material includes germanium.

Claims (35)

1. A method comprising:

providing a substrate comprising a first semiconductor material, wherein the substrate has a first region and a second region and the first semiconductor material comprises silicon;

forming a gate dielectric over the substrate in the first region;

forming a gate electrode over the gate dielectric;

forming a first semiconductor protective layer over the first region and the second region after forming the gate electrode;

removing portions of the first semiconductor protective layer in the second region to form openings;

forming a second semiconductor material in the openings, wherein the second semiconductor comprises germanium;

forming a second semiconductor protective layer over the second semiconductor in the second region;

patterning the first semiconductor protective layer in the first region to expose an area; and

forming a contact that is coupled to the area.

2. The method of claim 1 , wherein the forming the first semiconductor protective layer is performed after forming source/drain regions of a transistor.

3. The method of claim 1 , wherein the forming the first semiconductor protective layer comprises forming the first semiconductor protective layer comprising a dielectric.

4. The method of claim 1 , wherein the second semiconductor protective layer comprises silicon and nitrogen.

5. The method of claim 1 , wherein the forming the first semiconductor protective layer comprises forming silicon dioxide.

6. The method of claim 1 , wherein the forming the second semiconductor in the openings comprises selectively depositing epitaxial germanium.

7. The method of claim 1 , further comprising saliciding the area prior to forming the contact, implanting the second semiconductor material with a dopant, annealing the second semiconductor material after the implanting, and wherein the annealing is performed after the saliciding the area.

8. The method of claim 1 , further comprising implanting the second semiconductor with a dopant, annealing the second semiconductor material after the implanting, and wherein the annealing is performed before saliciding the area.

9. The method of claim 1 , wherein the forming the first semiconductor protective layer comprises depositing the first semiconductor protective layer.

10. A method comprising:

providing a substrate comprising silicon;

forming a transistor on the substrate;

forming a silicon protective layer over the substrate after forming the transistor;

exposing portions of the substrate, wherein the exposing comprises forming windows in the silicon protective layer;

forming a material comprising germanium in the windows;

forming a germanium protective layer over the substrate;

patterning the germanium protective layer and the silicon protective layer to expose an area comprising silicon; and

saliciding the area.

11. The method of claim 10 , wherein the forming the silicon protective layer is performed after forming source/drain regions of the transistor.

12. The method of claim 10 , wherein the forming the silicon protective layer comprises forming the silicon protective layer comprising a dielectric.

13. The method of claim 12 , wherein the forming the silicon protective layer comprises forming silicon dioxide.

14. The method of claim 10 , wherein the forming the material comprising germanium in the windows comprises selectively depositing epitaxial germanium.

15. The method of claim 10 , further comprising implanting the material comprising germanium with a dopant, annealing the material after the implanting, and wherein the annealing is performed after the saliciding the area.

16. The method of claim 10 , further comprising implanting the material comprising germanium with a dopant, annealing the material after the implanting, and wherein the annealing is performed before the saliciding the area.

17. The method of claim 10 wherein the germanium protective layer comprises silicon and nitrogen.

18. The method of claim 10 wherein the substrate is a silicon-on-insulator (SOI) substrate.

Assignments (18)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0655 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →