IP Library Granted Patent US 7,534,693
Granted Patent B2
US 7,534,693 · App. 11/326,524 · Granted May 19, 2009

Thin-film capacitor with a field modification layer and methods for forming the same

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Quick Facts
Patent No.
US 7,534,693
App. No.
11/326,524
Granted
May 19, 2009
Kind
B2
Abstract

A method for forming a capacitor includes providing a metal-containing bottom electrode, forming a capacitor insulator over the metal-containing bottom electrode, forming a metal-containing top electrode over the capacitor insulator, and forming a dielectric-containing field modification layer over the capacitor insulator and at least partially surrounding the metal-containing top electrode. Forming the dielectric-containing field modification layer may include oxidizing a sidewall of the metal-containing field modification layer. A barrier layer may be formed over the capacitor insulator prior to forming the metal-containing top electrode.

Claims (32)

1. A method of forming a capacitor comprising:

providing a workpiece having a first electrode;

forming a capacitor insulator layer over the first electrode;

forming an etch-stop layer over the capacitor insulator layer, wherein the etch-stop layer comprises an insulating material;

forming a metal-containing layer over the etch-stop layer;

etching the metal-containing layer to define a second electrode having a sidewall, wherein etching is terminated before exposing the capacitor insulator layer; and

exposing the workpiece to an oxidizing ambient after etching the metal-containing layer, wherein during exposing the workpiece to the oxidizing ambient, substantially all of the capacitor insulator layer is covered by the etch-stop layer, and after exposing the workpiece to the oxidizing ambient, a dielectric-containing field modification layer overlies the capacitor insulator and etch-stop layers and at least partially surrounds the second electrode.

2. The process of claim 1 , wherein the etch-stop layer comprises a barrier layer.

3. The process of claim 2 , wherein the etch-stop layer comprises an oxide.

4. The process of claim 3 , wherein the etch-stop layer comprises hafnium oxide or aluminum oxide.

5. The process of claim 1 , wherein the dielectric-containing field modification layer comprises tantalum pentoxide, tantalum oxynitride, titanium oxide, titanium oxynitride, aluminum oxide, or aluminum oxynitride.

6. The process of claim 4 , wherein the capacitor insulator layer comprises silicon dioxide, silicon nitride, tantalum pentoxide, or hafnium oxide.

7. The process of claim 1 , wherein exposing the workpiece to the oxidizing ambient is performed using a plasma oxidation.

8. The method of claim 7 , wherein the plasma oxidation is performed at a temperature in a range of approximately 200 to 400 degrees Celsius.

9. The method of claim 1 , wherein exposing the workpiece to the oxidizing ambient is performed using an oxygen or ozone source that produces free radicals.

10. The method of claim 1 , wherein exposing the workpiece to the oxidizing ambient comprises oxidizing a sidewall of the second electrode to form the dielectric-containing field modification layer.

11. The method of claim 1 , wherein exposing the workpiece to the oxidizing ambient results in a boundary between the dielectric-containing field modification layer and the second electrode, wherein the boundary forms an angle with respect to a bottom surface of the second electrode, the angle facing the second electrode and being greater than 90 degrees.

12. The method of claim 1 , wherein forming the dielectric-containing field modification layer has a thickness of at least 100 Angstroms.

13. The method of claim 12 , wherein the etch-stop layer has a thickness in a range of 10 to 100 Angstroms.

14. A method of forming a capacitor comprising:

providing a workpiece having a first electrode;

forming a capacitor insulator layer over the first electrode;

forming an etch-stop layer over the capacitor insulator layer, wherein the etch-stop layer comprises an insulating barrier layer, wherein the etch-stop layer has a different composition as compared to the capacitor insulator layer;

forming a metal-containing layer over the etch-stop layer;

etching the metal-containing layer to define a second electrode, wherein etching is terminated before exposing the capacitor insulator layer; and

oxidizing a sidewall of the second electrode to form an oxide-containing field modification layer that overlies the capacitor insulator and etch-stop layers and at least partially surrounds the second electrode, wherein during oxidizing, substantially all of the capacitor insulator layer is covered by the etch-stop layer.

15. The method of claim 14 , wherein the oxide-containing field modification layer comprises tantalum pentoxide, tantalum oxynitride, titanium oxide, titanium oxynitride, aluminum oxide, or aluminum oxynitride.

16. The method of claim 15 , wherein the capacitor insulator layer comprises silicon dioxide, silicon nitride, tantalum pentoxide, or hafnium oxide.

17. The method of claim 16 , wherein the etch-stop layer comprises hafnium oxide or aluminum oxide.

18. The method of claim 14 , wherein oxidizing the sidewall of the second electrode is performed using a plasma oxidation at a temperature in a range of approximately 200 to 400 degrees Celsius.

19. The method of claim 14 , wherein oxidizing the sidewall of the second electrode is performed using an oxygen or ozone source that produces free radicals.

20. The method of claim 14 , wherein oxidizing the sidewall of the second electrode results in a boundary between the oxide-containing field modification layer and the second electrode, wherein the boundary forms an angle with respect to a bottom surface of the second electrode, the angle facing the second electrode and being greater than 90 degrees.

Assignments (23)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0823 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Sep 23, 2009
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 023273/0099 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2006
From: ROBERTS, DOUGLAS R.; LUCKOWSKI, ERIC D.; RAUF, SHAHID; VENTZEK, PETER L.G.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 017445/0195 →