Method and apparatus for interconnecting portions of circuitry within a data processing system
View Patent ↗A method and apparatus for interconnecting circuit portions ( 12, 14, 16, 18, 20 ) within a data processing system ( 10 ) using a master/slave interfaces ( 30–37, 134 ) which may be configured by way of configuration registers ( 21–28, 156, 100 ). External address generation circuitry ( 140 ) and internal address generation circuitry ( 142 ) may be used to generate externally used addresses and internally used addresses, respectively. A circuit portion (e.g. 20 ) may have a plurality of interfaces ( 37, 134 ) which may operate as a slave interface (e.g. 134 ) or as a master interface (e.g. 37 ). A same master/slave interface structure and protocol (e.g. 30, 140, 142, 144, 28, 152 ) may be duplicated and individually configured to be used to communicate among all of the circuit portions ( 12, 14, 16, 18, 20 ) within a data processing system ( 10 ).
1. An integrated circuit, comprising:
a first interface and a second interface, wherein each of the first and second interface operate according to a same protocol and are capable of operating simultaneously;
configuration circuitry coupled to the first and second interface and capable of configuration each of the first and second interfaces as one of a master interface or a slave interface;
storage circuitry;
first address generation circuitry coupled to the first interface, said first address generation circuitry generating an external address when the first interface is configured as a master interface, wherein only a portion of the external address is provided via the first interface as a slave enable indicator; and
second address generation circuitry coupled to the first external address generation circuitry and the storage circuitry, said second address generation circuitry generating an internal address for accessing the storage circuitry.
2. The integrated circuit of claim 1 , further comprising:
third address generation circuitry coupled to the second interface, said third address generation circuitry generating a second external address when the second interface is configured as a master interface, wherein only a portion of the second external address is provided via the second interface as a second slave enable; and
fourth address generation circuitry coupled to the third external address generation circuitry and the storage circuitry, said fourth address generation circuitry generating a second internal addresses for accessing the storage circuitry.
3. The integrated circuit of claim 1 , further comprising:
processing circuitry, coupled to the storage circuitry, said processing circuitry processing data stored within the storage circuitry.
4. The integrated circuit of claim 1 , wherein the first interface comprises a plurality of input/output terminals and the second interface comprises a plurality of input/output terminals.
5. The integrated circuit of claim 1 , further comprising:
a plurality of input/output terminals; and
multiplexing circuitry coupled to the first and second interface, wherein the multiplexing circuitry selectively communicates signals to or from one of the first and second interface to the plurality of input/output terminals.
6. A data processor, comprising:
first interface;
configuration circuitry coupled to the first interface and capable of configuring the first interface as one of a master interface or a slave interface;
storage circuitry;
first address generation circuitry coupled to the first interface, said first address generation circuitry generating an external address when the first interface is configured as a master interface and providing only a portion of said external address via the first interface, wherein the portion of the external address provides a slave enable indicator; and
second address generation circuitry coupled to the first external address generation circuitry and to the storage circuitry, said second address generation circuitry generating an internal address for accessing the storage circuitry.
7. The data processor of claim 6 , wherein the external address is independent from the internal address.
8. The data processor of claim 6 , wherein the first address generation circuitry operates independently of the second address generation circuitry.
9. The data processor of claim 8 , wherein the first address generation circuitry and the second address generation circuitry operate using different clock rates.
10. The data processor of claim 8 , wherein the first address generation circuitry and the second address generation circuitry operate using different data burst sizes.
11. An integrated circuit comprising the data processor of claim 6 .
12. A data processing system, comprising:
a first data processor having a first internal address generator and a first interface configured to operate as a master, wherein:
the first internal address generator generates a first internal address; and
the first data processor provides data via the first interface corresponding to the first internal address or receives data via the first interface to be stored at the first internal address; and
a second data processor having a second internal address generator, and a second interface configured to operate as a slave, the second interface directly connected to the first interface, and wherein:
the second internal address generator generates a second internal address; and
the second data processor receives data from the first data processor to be stored at the second internal address or provides data stored at the second internal address to the first data processor.
13. The data processing system of claim 12 , wherein the first data processor comprises an external address generator which provides a slave enable via the first interface.
14. The data processing system of claim 13 , wherein the external address generator generates an external address and provides only a portion of the external address via the first interface, wherein the portion of the external address provides the slave enable.
15. The data processing system of claim 12 , wherein the first internal address is independent from the second internal address.
16. The data processing system of claim 12 , wherein the first interface comprises a plurality of input/output terminals and the second interface comprises a plurality of input/output terminals.
17. The data processing system of claim 12 , further comprising:
a third data processor having second storage circuitry and a third interface configured to operate as a slave, the third interface directly connected to the first interface, wherein:
the third data processor generates a third internal address corresponding to an address within the second storage circuitry; and
the third data processor receives data from the first data processor to be stored at the third internal address or provides the data stored at the third internal address to the first data processor.
18. The data processing system of claim 12 , wherein the second data processor further comprises a third interface operating using a same protocol as the first and second interfaces and configured to operate as one of a master or a slave, the data processing system further comprising:
a third data processor having a fourth interface directly connected to the third interface and operating using the same protocol as the first, second, and third interfaces, and
wherein the fourth interface is configured to operate as one of a master or a slave.
19. The data processing system of claim 12 , wherein the first data processor comprises a first configuration register, the configuration register providing master/slave configuration information and data rate information corresponding to the first interface, and wherein the second data processor comprises a second configuration register, the second configuration register providing master/slave configuration information and data rate information corresponding to the second interface.
20. An integrated circuit comprising the first and second data processors as claimed in claim 13 .
21. A method for communicating data, comprising:
generating an external address and a first internal address within a first data processor;
providing only a portion of the external address from an interface of the first data processor directly to an interface of a second data processor, wherein the portion of the external address provides a slave enable indicator;
based on the slave enable indicator, selectively generating a second internal address within a second data processor, corresponding to storage circuitry within the second data processor; and
based on the slave enable indicator, selectively providing data stored at the second internal address from the interface of the second data processor directly to the interface of the first data processor and storing the data in the first data processor at the first internal address.
22. The method of claim 21 , further comprising:
providing only a second portion of the external address from the interface of the first data processor directly to an interface of a third data processor, wherein the second portion of the external address provides a second slave enable indicator; and
based on the second slave enable indicator, selectively generating a third internal address within a third data processor, corresponding to storage circuitry within the third data processor; and
based on the slave enable indicator, selectively providing data stored at the third internal address from the interface of the third data processor directly to the interface of the first data processor and storing the data in the first data processor at the first internal address.
23. The method of claim 21 , further comprising:
based on the slave enable indicator, selectively providing a transfer request to the first data processor, prior to providing data stored at the second internal address.
24. The method of claim 21 , wherein a remaining portion of the external address is not provided by the first data processor to the second data processor.
25. A method for communication data, comprising:
generating an external address and a first internal address within a first data processor;
providing only a portion of the external address via an interface of the first data processor, wherein the portion of the external address provides a slave enable indicator;
providing data stored at the first internal address via an interface of the first circuit portion;
based on the slave enable indicator, selectively generating a second internal address within a second data processor, corresponding to storage circuitry within the second circuit portion; and
based on the slave enable indicator, selectively receiving the data stored at the first internal address at an interface of the second circuit portion, directly from the interface of the first data processor and storing the received data within the storage circuitry of the second data processor at the second internal address.
26. The method of claim 25 , further comprising:
providing only a second portion of the external address from the interface of the first data processor directly to an interface of a third data processor, wherein the second portion of the external address provides a second slave enable indicator; and
based on the second slave enable indicator, selectively generating a third internal address within a third data processor, corresponding to storage circuitry within the third data processor; and
based on the slave enable indicator, selectively receiving the data stored at the first internal address at an interface of the third circuit portion, directly from the interface of the first data processor and storing the received data within the storage circuitry of the third data processor at the third internal address.
27. The method of claim 25 , further comprising:
based on the slave enable indicator, selectively providing a transfer request to the first data processor, prior to receiving data stored at the first internal address.
28. The method of claim 25 , wherein a remaining portion of the external address is not provided from the first data processor to the second data processor.