Field plate transistor with reduced field plate resistance
View Patent ↗In one example embodiment, a transistor ( 100 ) is provided. The transistor ( 100 ) comprises a source ( 10 ), a gate ( 30 ), a drain ( 20 ), and a field plate ( 40 ) located between the gate ( 30 ) and the drain ( 20 ). The field plate ( 40 ) comprises a plurality of connection locations ( 47 ) and a plurality of electrical connectors ( 45 ) connecting said plurality of connection locations ( 47 ) to a potential.
1. A transistor, the transistor comprising:
a source;
a gate;
a drain;
a field plate located between the gate and the drain,
wherein said field plate comprises a plurality of connection locations; and
a plurality of electrical connectors connecting said plurality of connection locations to a potential.
2. The transistor of claim 1 , wherein said field plate comprises a highly resistive material.
3. The transistor of claim 2 , wherein said highly resistive material comprises Titanium Tungsten Nitride.
4. The transistor of claim 1 , wherein said potential comprises a source potential.
5. The transistor of claim 1 , wherein said potential comprises a ground potential.
6. The transistor of claim 1 , wherein said potential comprises a gate potential.
7. The transistor of claim 1 , wherein said plurality of connection locations are essentially equidistant from one another.
8. The transistor of claim 1 , wherein said plurality of electrical connectors are located in a region having electrical activity that is reduced in comparison to the electrical activity designed for a neighboring region.
9. The transistor of claim 8 , wherein said plurality of electrical connectors and said field plate comprises highly resistive material.
10. The transistor of claim 1 , wherein said plurality of electrical connectors are located in an active region.
11. A system for reduction of gate-to-drain capacitance in a transistor, the system comprising:
means for connecting a plurality of locations on a field plate finger to a potential, the field plate finger being located between a drain of a transistor and a source of the transistor; and
means for applying a voltage to the means for connecting.
12. A system as in claim 11 , wherein said means for connecting comprises a set of electrical conductors spaced along the field plate finger.
13. A system as in claim 12 , wherein said set of electrical conductors are spaced at a plurality of essentially equidistant locations along the field plate finger.
14. A system as in claim 12 , wherein said means for applying comprises an electrical conductor between the means for connecting and a potential.
15. A system as in claim 14 , wherein said potential comprises a source potential.
16. A system as in claim 14 , wherein said potential comprises a ground potential.
17. A system as in claim 14 , wherein said potential comprises a gate potential.
18. A system as in claim 11 , wherein said means for connecting is located in a region of electrical activity that is substantially less than a designed electrical activity level of a neighboring region.
19. The transistor of claim 1 wherein:
the field plate extends in a first direction;
the plurality of connectors extend in a second direction, the second direction being perpendicular to the first direction.
20. The transistors of claim 1 wherein the field plate and the plurality of connectors are located in the same plane as the field plate.