Granted Patent B2

US 7,233,539 · App. 11/135,963 · Granted Jun 19, 2007

Abstract

Claims (42)

1. A non-volatile memory cell comprising:

a fuse having a first terminal coupled to a first power supply voltage terminal, and a second terminal;

a first transistor having a first current electrode coupled to said second terminal of said fuse, a control electrode for receiving a control signal, and a second current electrode;

a first inverter having an input terminal coupled to said second current electrode of said first transistor, and an output terminal for providing an output of the non-volatile memory cell; and

a second inverter having an input terminal coupled to said output terminal of said first inverter, and an output terminal coupled to said input terminal of said first inverter.

2. The non-volatile memory cell of claim 1 , further comprising:

a second transistor having a first current electrode coupled to said input terminal of said first inverter, a control electrode for receiving said control signal, and a second current electrode coupled to a second power supply voltage terminal.

3. The non-volatile memory cell of claim 1 , further comprising:

a second transistor having a first current electrode coupled to said second terminal of said fuse, a control electrode for receiving a program signal, and a second current electrode coupled to a second power supply voltage terminal.

4. The non-volatile memory cell of claim 1 , wherein said first inverter comprises:

a second transistor having a first current electrode coupled to said first power supply voltage terminal, a second current electrode coupled to said output terminal of said first inverter and a control electrode coupled to said input terminal of said first inverter; and

a third transistor having a first current electrode coupled to said output terminal of said first inverter, a second current electrode coupled to a second power supply voltage terminal and a control electrode coupled to said input terminal of said first inverter.

5. The non-volatile memory cell of claim 4 , wherein said second transistor is a p-channel transistor and said third transistor is an n-channel transistor.

6. The non-volatile memory cell of claim 4 , wherein said second inverter comprises:

a fourth transistor having a first current electrode coupled to said first power supply voltage terminal, a second current electrode coupled to said input terminal of said first inverter and a control electrode coupled to said output terminal of said first inverter; and

a fifth transistor having a first current electrode coupled to said input node of said first inverter, a second current electrode coupled to said second power supply voltage and a control electrode coupled to said output terminal of said first inverter.

7. The non-volatile memory cell of claim 6 , wherein said fourth transistor is a p-channel transistor and said fifth transistor is an n-channel transistor.

8. A non-volatile memory cell comprising:

a static latch having a first terminal and a second terminal;

a first transistor having a first current electrode coupled to said first terminal of said static latch; and

a fusible element having a first terminal coupled to a second current electrode of said first transistor and a second terminal coupled to a first power supply voltage terminal.

9. The non-volatile memory cell of claim 8 , further comprising:

a fusible element programming circuit coupled to said first terminal of said fusible element.

10. The non-volatile memory cell of claim 9 , wherein said fusible element programming circuit comprises a second transistor having a first current electrode coupled to said first terminal of said fusible element and a second current electrode coupled to a second power supply voltage terminal.

11. The non-volatile memory cell of claim 8 , further comprising:

a cell preset circuit coupled to a control electrode of said first transistor.

12. The non-volatile memory cell of claim 11 , wherein said cell preset circuit comprises a second transistor having a first current electrode coupled to said first terminal of said static latch and a second current electrode coupled to a second power supply voltage terminal.

13. The non-volatile memory cell of claim 8 , wherein said static latch comprises:

a first inverter having an input coupled to said first terminal of said static latch and an output coupled to said second terminal of said static latch; and

a second inverter having an input coupled to said output of said first inverter and an output coupled to said input of said first inverter.

14. The non-volatile memory cell of claim 13 , wherein said first inverter comprises a second transistor having a first current electrode coupled to said first power supply voltage terminal and a second current electrode coupled to an output of said first inverter and a control electrode coupled to an input of said first inverter and a third transistor having a first current electrode coupled to said output of said first inverter and a second current electrode coupled to a second power supply voltage terminal and a control electrode coupled to said input of said first inverter.

15. The non-volatile memory cell of claim 13 , wherein said second inverter comprises a fourth transistor having a first current electrode coupled to said first power supply voltage terminal and a second current electrode coupled to said input of said first inverter and a control electrode coupled to said output of said first inverter and a fifth transistor having a first current electrode coupled to said input of said first inverter and a second current electrode coupled to said second power supply voltage terminal and a control electrode coupled to said output of said first inverter.

16. The non-volatile memory cell of claim 13 , further comprising:

a trimming circuit coupled to said second terminal of said static latch to adjust the characteristics of an integrated circuit.

17. A method for reading a non-volatile memory cell comprising the steps of:

presetting a static latch circuit to a first state;

selectively setting said latch circuit to a second state in response to a condition of a fuse;

providing an output of the non-volatile memory cell representative of a state of said latch circuit after said step of selectively setting; and

trimming an integrated circuit based on the output of said latch.

18. The method of claim 17 , further comprising:

programming said fuse.

19. The method of claim 18 , wherein programming said fuse comprises applying a current to said fuse.

Assignments (30)