Model correspondence method and device
View Patent ↗A method and device for determining memory element and intermediate point correspondences between design models is disclosed. The method includes developing graph representations of two circuit design models of an electronic device. The circuit design models each include input and output nodes corresponding to input and output nodes of the electronic device. The circuit design models also include memory and intermediate nodes corresponding to memory elements and intermediate points, respectively of the electronic device. An intermediate point represents a point between memory elements of the electronic device, and so can represent logic gates or other modules of the device. Memory elements and intermediate points can be referred to collectively as circuit elements. Nodes in the graph representation represent inputs, outputs, memory elements or intermediate points in the design models. A correspondence between the circuit elements in circuit design models is determined based on the graph representations.
1. A method comprising:
associating at a processor a first label to a first vertex associated with a first circuit design model, wherein the first vertex is representative of a first circuit element of the first circuit design model;
associating at the processor a first set of labels to a plurality of input and output nodes associated with the first circuit design model, wherein the plurality of input and output nodes is representative of a first set of inputs and outputs of the first circuit design model;
associating at the processor a second set of labels to a plurality of vertices associated with the first circuit design model, wherein the plurality of vertices is associated with a plurality of circuit elements coupled to the first circuit element of the first circuit design model;
determining at the processor a second label for the first vertex based on the first set of labels and the second set of labels; and
determining at the processor a first correspondence between the first circuit design model and a second circuit design model based on the second label for the first vertex;
associating at the processor a third label to a second vertex associated with the second circuit design model, wherein the second vertex is representative of a first circuit element of the second circuit design model;
associating at the processor the first set of labels to a plurality of input and output nodes associated with the second circuit design model, wherein the plurality of input and output nodes is representative of a set of inputs and outputs of the second circuit design model;
associating at the processor a third set of labels to a plurality of vertices associated with the second circuit design model, wherein the plurality of vertices is associated with a plurality of circuit elements coupled to the first circuit element of the second circuit design model;
determining at the processor a fourth label for the second vertex based on the first set of labels and the third set of labels;
wherein the first correspondence between the first circuit design model and the second circuit design model is further based on the fourth label.
2. The method of claim 1 , further comprising:
associating at the processor a third label to an edge between the first vertex and one of the plurality of vertices, associated with the first circuit design model, wherein the edge is representative of a logic path between the first circuit element and a second circuit element of the first circuit design model;
wherein the second label is further based on the third label.
3. The method of claim 2 , wherein the third label is based on a direction of the logic path.
4. The method of claim 1 , further comprising:
associating at the processor a third label to the first vertex based on the first correspondence.
5. The method of claim 4 , wherein the third label is a prime number.
6. The method of claim 4 , further comprising:
determining at the processor a label for a second vertex of the first circuit design model based on the third label and the first set of labels.
7. The method of claim 1 , wherein the first circuit element is a storage element of the first circuit design model.
8. The method of claim 1 , wherein the first circuit element is an intermediate point of the first circuit design model.
9. The method of claim 1 , wherein the first circuit model is selected from the group consisting of a Register Transfer Level (RTL) model, a transistor circuit level model, and a gate level model.
10. The method of claim 1 , further comprising:
determining at the processor an Nth set of labels for the first set of vertices by iteratively calculating N sets of labels for the first set of vertices, wherein the Nth set of labels is calculated based on the first set of labels and the N−1 set of labels.
11. The method of claim 10 , further comprising:
a) determining at the processor an N+1th set of labels for the first set of vertices by iteratively calculating N+1 sets of labels for the first set of vertices, wherein the N+1th set of labels is calculated based on the first set of labels and the Nth set of labels;
b) detecting at the processor a match between the N+1th set of labels to the Nth set of labels;
c) incrementing N; and
d) repeating a) through c) until a predetermined number of matches have been detected.
12. The method of claim 1 , further comprising:
generating at the processor the first set of vertices based on a data file associated with the first circuit design model;
generating at the processor the plurality of input and output nodes based on the data file.
13. A computer readable medium tangibly embodying a program of instructions to be executed by a processor, the program of instructions comprising:
instructions to associate a first label to a first vertex associated with a first circuit design model, wherein the first vertex is representative of a first circuit element of the first circuit design model;
instructions to associate a first set of labels to a plurality of input and output nodes associated with the first circuit design model, wherein the plurality of input and output nodes is representative of a first set of inputs and outputs of the first circuit design model;
instructions to associate a second set of labels to a plurality of vertices associated with the first circuit design model, wherein the plurality of vertices is associated with a plurality of circuit elements coupled to the first circuit element of the first circuit design model;
instructions to determine a second label for the first vertex based on the first set of labels and the second set of labels; and
instructions to determine a first correspondence between the first circuit design model and a second circuit design model based on the second label for the first vertex;
instructions to associate a third label to a second vertex associated with the second circuit design model, wherein the second vertex is representative of a first circuit element of the second circuit design model;
instructions to associate the first set of labels to a plurality of input and output nodes associated with the second circuit design model, wherein the plurality of input and output nodes is representative of a set of inputs and outputs of the second circuit design model;
instructions to associate a third set of labels to a plurality of vertices associated with the second circuit design model, wherein the plurality of vertices is associated with a plurality of circuit elements coupled to the first circuit element of the second circuit design model;
instructions to determine a fourth label for the second vertex based on the first set of labels and the third set of labels; and
wherein the first correspondence between the first circuit design model and the second circuit design model is further based on the second label and the fourth label.
14. The computer readable medium of claim 13 , further comprising:
instructions to associate a third label to an edge between the first vertex and one of the plurality of vertices, associated with the first circuit design model, wherein the edge is representative of a logic path between the first circuit element and a second circuit element of the first circuit design model;
wherein the second label is further based on the third label.
15. The computer readable medium of claim 14 , wherein the third label is based on a direction of the logic path.
16. The computer readable medium of claim 13 , further comprising:
instructions to associate a third label to the first vertex based on the first correspondence.
17. The computer readable medium of claim 16 , wherein the third label is a prime number.
18. The computer readable medium of claim 16 , further comprising:
instructions to determine a label for a second vertex of the first circuit design model based on the third label and the first set of labels.