IP Library Granted Patent US 6,967,158
Granted Patent B2
US 6,967,158 · App. 10/384,398 · Granted Nov 22, 2005

Method for forming a low-k dielectric structure on a substrate

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Quick Facts
Patent No.
US 6,967,158
App. No.
10/384,398
Granted
Nov 22, 2005
Kind
B2
Abstract

The present invention provides a method for forming a low-k dielectric structure on a substrate 10 that includes depositing, upon the substrate, a dielectric layer 12. A multi-film cap layer 18 is deposited upon the dielectric layer. The multi-film cap layer includes first 181 and second 182 films, with the second film being disposed between the dielectric layer and the first film. The first film typically has a removal rate associated therewith that is less than the removal rate associated with the second film. A deposition layer 20 is deposited upon the multi-film cap layer and subsequently removed. The properties of the multi-film cap layer are selected so as to prevent the dielectric layer from being exposed/removed during removal of the deposition film. In this manner, a deposition layer, having variable rates of removal, such as copper, may be planarized without damaging the underlying dielectric layer.

Claims (34)

1. A method of forming a low-k dielectric structure on a substrate, said method comprising:

depositing, upon said substrate, a dielectric layer;

forming on said dielectric layer, a multi-film cap layer, said multi-film cap layer comprising first and second films, with said second film being disposed between said dielectric layer and said first film;

forming a deposition layer upon said multi-film cap layer, wherein said multi-film cap layer and said dielectric layer define a film stack; and

removing portions of said film stack, said portions comprising said deposition layer wherein said multi-film cap layer has properties to prevent said dielectric layer from being removed upon removal of said deposition film;

wherein removing further comprises removing substantially all of said first film.

2. The method as recited in claim 1 wherein removing portions further comprises providing said first film with properties to prevent said second film from being removed during removal of said deposition layer.

3. The method as recited in claim 1 wherein forming on said dielectric layer further comprises providing said first film with a dielectric constant greater than a dielectric constant associated with said second film.

4. The method as recited in claim 1 wherein said properties comprise removal rate and film thickness.

5. The method as recited in claim 1 wherein forming on said dielectric layer further comprises forming said first film from materials selected from a set consisting essentially of TEOS, SiON and SiN and forming said deposition layer further comprises forming said deposition layer from a conductive material.

6. The method as recited in claim 1 wherein depositing further comprises depositing an OSG layer having a first porosity associated therewith and forming on said dielectric layer further comprises forming said second film from an additional OSG layer having a second porosity associated therewith, with said second porosity being less than said first porosity.

7. The method as recited in claim 1 wherein removing said portions comprises planarizing said film stack employing a chemical mechanical polishing technique and providing said first film and said second film with a removal rate, with the removal rate of said first film being substantially less than a removal rate of said deposition layer.

8. The method as recited in claim 1 further comprising forming a trench into said dielectric layer extending therethrough, wherein forming said deposition layer further comprises depositing a conductive material onto said substrate, a first sub-portion of said conductive material filling said trench to form a conductive contact.

9. A method of forming a low-k dielectric structure upon a substrate, said method comprising:

depositing, upon said substrate, a dielectric layer having a first porosity associated therewith;

forming on said dielectric layer, a multi-film cap layer, said multi-film cap layer comprising a sacrificial film having a second porosity associated therewith and a second film having a third porosity associated therewith, with said first porosity being greater than said second and third porosities and said third porosity being greater than said second porosity, said second film being disposed between said dielectric layer and said sacrificial film;

forming a deposition layer upon said multi-film cap layer, with said deposition layer, said multi-film cap layer and said dielectric layer defining a film stack; and

removing portions of said film stack including substantially all of said sacrificial film, with said second and third porosities and a thickness of said first and second films being established to allow removal of said deposition layer from said film stack without removing said dielectric layer.

10. The method as recited in claim 9 wherein forming on said dielectric layer comprises providing said sacrificial film with a dielectric constant greater than a dielectric constant associated with said second film.

11. The method as recited in claim 9 wherein said properties comprise removal rate and film thickness.

12. The method as recited in claim 11 wherein depositing comprises depositing an OSG layer; forming on said dielectric layer further comprises forming said sacrificial film from materials from a set consisting essentially of TEOS, SiON and SiN and forming said second film from an additional OSG layer; and forming said deposition layer comprises forming said deposition layer of copper.

13. The method as recited in claim 9 wherein removing said portions further comprises planarizing said film stack employing a chemical mechanical polishing technique providing said sacrificial film and said second film with a removal rate, with the removal rate of said sacrificial film being substantially less than a removal rate of said deposition layer.

14. The method as recited in claim 9 further comprising forming a trench into said dielectric layer, wherein forming said deposition layer further comprises depositing copper material onto said substrate, with a first sub-portion of said copper material filling said trench to form a contact.

15. A semiconductor fabrication method for forming a dielectric film stack, comprising:

depositing a low k dielectric layer;

forming a capping layer on the low k layer;

depositing a sacrificial layer on the capping layer;

forming a trench through the sacrificial layer, the capping layer, and the low k dielectric layer;

depositing a conductive layer on the sacrificial layer and in the trench; and

removing portions of the conductive layer exterior to the trench, wherein said removing includes removing the sacrificial layer wherein a dielectric constant of the film stack is independent of a dielectric constant of the sacrificial layer.

16. The method of claim 15 , further comprising prior to depositing the low k dielectric, depositing a silicon nitride passivation layer and further wherein depositing the low k dielectric comprises depositing the low k dielectric on the passivation layer.

17. The method of claim 16 , wherein the sacrificial layer is a TEOS layer.

18. The method of claim 17 , wherein depositing the low k dielectric comprises depositing an organosilicate glass (OSG) and further wherein depositing the capping layer comprises depositing a second OSG layer and subsequently densifying the second OSG layer.

19. The method of claim 18 , wherein depositing the conductive layer comprises depositing copper and wherein removing portions of the conductive layer comprises chemical mechanical polishing the conductive layer.

Assignments (23)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
AFFIRMATION OF PATENT ASSIGNMENT Recorded Aug 18, 2009
From: ADVANCED MICRO DEVICES, INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 023119/0083 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2004
From: MOTOROLA, INC
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 015360/0718 →