Capped dual metal gate transistors for CMOS process and method for making the same
View Patent ↗A first gate ( 120 ) and a second gate ( 122 ) are preferably PMOS and NMOS transistors, respectively, formed in an n-type well ( 104 ) and a p-type well ( 106 ). In a preferred embodiment first gate ( 120 ) includes a first metal layer ( 110 ) of titanium nitride on a gate dielectric ( 108 ), a second metal layer ( 114 ) of tantalum silicon nitride and a silicon containing layer ( 116 ) of polysilicon. Second gate ( 122 ) includes second metal layer ( 114 ) of a tantalum silicon nitride layer on the gate dielectric ( 108 ) and a silicon containing layer ( 116 ) of polysilicon. First spacers ( 124 ) are formed adjacent the sidewalls of the gates to protect the metals from chemistries used to remove photoresist masks during implant steps. Since the chemistries used are selective to polysilicon, the spacers ( 124 ) need not protect the polysilicon capping layers, thereby increasing the process margin of the spacer etch process. The polysilicon cap also facilitates silicidation of the gates.
1. A semiconductor device comprising:
a semiconductor substrate having a first well and a second well, wherein the first well has a first conductivity type and the second well has a second conductivity type different than the first conductivity type;
a gate dielectric over at least a portion of a first well and a portion of a second well;
a first gate over the first well and the gate dielectric and comprising a titanium nitride layer, a first tantalum silicon nitride layer, and a first conductive silicon-containing layer, wherein the titanium nitride layer is in physical contact with the gate dielectric; and
a second gaze over the second well and the gate dielectric and comprising a tantalum silicon nitride layer and a conductive silicon-containing layer, wherein the tantalum silicon nitride layer of the second gate is in physical contact with the gate dielectric.
2. The semiconductor device of claim 1 , further comprising first spacers adjacent sidewalls of the first gate and the second gate and second spacers adjacent the first spacers.
3. The semiconductor device of claim 2 , wherein the first spacers expose a portion of the sidewalls of the conductive silicon-containing layer of the first gate.
4. The semiconductor device of claim 2 , further comprising an oxide liner between the first spacers and the second spacers.
5. The semiconductor device of claim 2 , wherein the first spacers are thinner than the second spacers.
6. The semiconductor device of claim 5 , wherein the first spacers have a maximum thickness of approximately 50 to 200 angstroms.
7. The semiconductor device of claim 1 , wherein the conductive silicon-containing layer is a material selected from the group consisting of silicon and silicon germanium.
8. The semiconductor device of claim 1 , further comprising a silicide over the conductive silicon-containing layer in both the first gate and the second gate.
9. The semiconductor device of claim 1 , wherein the first well is n-type and the second well is p-type.