IP Library Granted Patent US 7,285,452
Granted Patent B2
US 7,285,452 · App. 11/351,518 · Granted Oct 23, 2007

Method to selectively form regions having differing properties and structure

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,285,452
App. No.
11/351,518
Granted
Oct 23, 2007
Kind
B2
Abstract

A semiconductor device is formed having two physically separate regions with differing properties such as different surface orientation, crystal rotation, strain or composition. In one form a first layer having a first property is formed on an insulating layer. The first layer is isolated into first and second physically separate areas. After this physical separation, only the first area is amorphized. A donor wafer is placed in contact with the first and second areas. The semiconductor device is annealed to modify the first of the first and second separate areas to have a different property from the second of the first and second separate areas. The donor wafer is removed and at least one semiconductor structure is formed in each of the first and second physically separate areas. In another form, the separate regions are a bulk substrate and an electrically isolated region within the bulk substrate.

Claims (43)

1. A method of forming a semiconductor device comprising:

providing an insulating layer;

forming a first layer on the insulating layer, the first layer having a first property;

separating the first layer into first and second separate areas which have no surfaces in contact with each other and electrically isolating the first and second separate areas;

after separating the first layer, amorphizing only the first of the first and second separate areas;

applying a donor wafer overlying and in contact with the first and second areas;

annealing the semiconductor device to modify the first of the first and second separate areas to have a different property from the second of the first and second separate areas;

removing the donor wafer; and

forming at least one semiconductor structure in each of the first and the second of the first and second separate areas.

2. The method of claim 1 further comprising:

providing the donor wafer as a wafer having at least one of differing strain, differing composition, differing surface orientation or differing crystal rotation from the second portion of the first layer.

3. The method of claim 1 wherein the second separate area of the first layer has a first surface orientation, and the donor wafer and the first separate area of the first layer has a second surface orientation differing from the first surface orientation.

4. The method of claim 1 further comprising:

providing a substrate underlying the insulating layer, wherein the second separate area of the first layer has a surface orientation of either (110) or (100), and the donor layer has a surface orientation of (100) or (110) depending upon the surface orientation of second separate area of the first layer.

5. The method of claim 1 wherein the first separate area of the first layer has a crystal rotation of (110) or (100) and the second separate area of the first layer has a crystal rotation having whichever value of (110) or (100) the first separate area of the first layer does not have.

6. The method of claim 1 wherein removing the donor wafer further comprises:

cleaving a first portion of the donor wafer along a lateral boundary comprising atoms of a predetermined composition; and

removing a remaining second portion of the donor wafer from the semiconductor device.

7. The method of claim 1 wherein the removing is performed before said annealing of the semiconductor device to modify the first of the first and second separate areas.

8. The method of claim 1 further comprising electrically isolating the first and second separate areas with an oxide material and forming the donor wafer by bonding the donor wafer to the first and second separate areas and the oxide material, the donor wafer comprising a lateral region having atomic irregularities which permit ready cleaving of the donor wafer along the lateral region.

9. A method of forming a semiconductor device comprising:

providing an insulating layer;

forming a first layer on the insulating layer, the first layer having a first crystal orientation;

separating the first layer into physically separate first and second separate areas and electrically isolating the first and second separate areas with a dielectric region;

after separating the first layer, amorphizing only the first of the first and second separate areas;

bonding a substrate layer of material to be in contact with the first and second areas and the dielectric region, the substrate layer of material having a second crystal orientation that differs from the first crystal orientation;

annealing the semiconductor device to modify the first of the first and second separate areas to have the second crystal orientation of the substrate layer of material;

removing the substrate layer of material; and

forming at least one semiconductor structure in each of the first and the second of the first and second separate areas.

10. The method of claim 9 wherein removing the substrate layer of material further comprises:

removing a portion of the substrate layer of material prior to said annealing and removing a remainder of the substrate of material after said annealing.

11. The method of claim 9 wherein removing the substrate layer of material further comprises:

removing a first portion of the substrate layer of material by cleaving the substrate layer of material along a lateral edge defined by a presence of differing atomic structure; and

removing a second portion of the substrate layer of material by chemical mechanical polishing the second portion.

12. A method of forming a semiconductor device comprising:

providing a bulk substrate having a first property;

forming an isolation region within the bulk substrate;

forming at least one region of amorphous semiconductor material within the isolation region;

applying a donor wafer overlying and in contact with an exposed surface of the bulk substrate, the isolation region and the at least one region of amorphous semiconductor material within the isolation region, the donor wafer having a second property which differs from the first property;

annealing the semiconductor device to transfer the second property of the donor wafer to the at least one region of amorphous semiconductor material within the isolation region;

removing the donor wafer; and

forming at least one semiconductor structure in the at least one region of amorphous semiconductor material within the isolation region.

13. The method of claim 12 wherein the first property and second property both comprise at least one of strain, composition, surface orientation or crystal rotation.

Assignments (23)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0670 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Jul 11, 2008
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 021217/0368 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2006
From: SADAKA, MARIAM G.; NGUYEN, BICH-YEN; THEAN, VOON-YEW; WHITE, TED R.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 017567/0939 →