Method and apparatus for performance enhancement in an asymmetrical semiconductor device
View Patent ↗A method and apparatus is presented that provides performance enhancement in a semiconductor device. In one embodiment, a first current region ( 64, 76, 23 ), a channel region and a second current region ( 75, 33, 66 ) are adjacent each other. The second current region ( 75, 33, 66 ) has a content of a first element of an alloy greater than a content of the first element in the first current region ( 64, 76, 23 ), wherein the second current region ( 75, 33, 66 ) has a content of the first element greater than a content of the first element in the channel region, the alloy further comprises a second element, the first element has a first valence number, and the second element has a second valence number. Furthermore, the sum of the first valence number and the second valence number is eight.
1. A semiconductor device comprising:
a semiconductor substrate;
a first current region, wherein at least a portion of the first current region is within the semiconductor substrate;
a channel region horizontally adjacent at least a portion of the first current region; and
a second current region horizontally adjacent the channel region, wherein:
the second current region has a content of a first element of an alloy greater than a content of the first element in the first current region;
the second current region has a content of the first element greater than a content of the first element in the channel region;
the alloy further comprises a second element;
the first element has a first valence number;
the second element has a second valence number, and
a sum of the first valence number and the second valence number is eight.
2. The semiconductor device of claim 1 , wherein the alloy is a semiconductor material.
3. The semiconductor device of claim 1 , wherein the first current region is an elevated source region and the second current region is an elevated drain region.
4. The semiconductor device of claim 1 , wherein the channel region comprises a third element and the third element is the same as the second element of the alloy.
5. The semiconductor device of claim 4 , wherein the channel region and the semiconductor substrate are a same material.
6. The semiconductor device of claim 4 , wherein the channel region and the semiconductor substrate are different materials.
7. The semiconductor device of claim 1 , wherein the second current region is a drain region.
8. The semiconductor device of claim 7 , wherein the first element is germanium and the second element is silicon.
9. The semiconductor device of claim 8 , wherein the channel region is P-type.
10. The semiconductor device of claim 7 , wherein the first element is carbon and the second element is silicon.
11. The semiconductor device of claim 10 , wherein the channel region is N-type.
12. The semiconductor device of claim 11 , wherein the first current region comprises a first region within the semiconductor substrate and a second region over the first region, wherein the second region comprises the alloy and the first region comprises the second element.
13. A semiconductor device comprising:
a semiconductor substrate;
a first current region, wherein at least a portion of the first current region is within the semiconductor substrate;
a second current region, wherein:
at least a portion of the second current region is within the semiconductor substrate;
the second current region has a content of a first element of an alloy greater than a content of the first element in the first current region;
the alloy further comprises a second element;
the first element has a first valence number;
the second element has a second valence number; and
a sum of the first valence number and the second valence number is eight; and
a channel region between the first current region and the second current region, wherein the channel region is substantially devoid of the first element.
14. The semiconductor device of claim 13 , wherein the alloy is a semiconductor material.
15. The semiconductor device of claim 13 , wherein the channel region comprises a third element and the third element is the same as the second element of the alloy.
16. The semiconductor device of claim 15 , wherein the channel region and the semiconductor substrate are a same material.
17. The semiconductor device of claim 15 , wherein the channel region and the semiconductor substrate are different materials.
18. The semiconductor device of claim 13 , wherein the second current region is a drain region.
19. The semiconductor device of claim 18 , wherein the first element is germanium and the second element is silicon.
20. The semiconductor device of claim 19 , wherein the channel region is P-type.
21. The semiconductor device of claim 18 , wherein the first element is carbon and the second element is silicon.
22. The semiconductor device of claim 21 , wherein the channel region is N-type.
23. The semiconductor device of claim 13 , wherein the first current region is an elevated source region and the second current region is an elevated drain region.
24. The semiconductor device of claim 23 , wherein the first current region comprises a first region within the semiconductor substrate and a second region over the first region, wherein the second region comprises the alloy and the first region comprises the second element.