IP Library Granted Patent US 7,282,426
Granted Patent B2
US 7,282,426 · App. 11/092,289 · Granted Oct 16, 2007

Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof

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Quick Facts
Patent No.
US 7,282,426
App. No.
11/092,289
Granted
Oct 16, 2007
Kind
B2
Abstract

A method for forming a semiconductor device including forming a semiconductor substrate; forming a gate electrode over the semiconductor substrate having a first side and a second side, and forming a gate dielectric under the gate electrode. The gate dielectric has a first area under the gate electrode and adjacent the first side of the gate electrode, a second area under the gate electrode and adjacent the second side of the gate electrode, and a third area under the gate electrode that is between the first area and the second area, wherein the first area is thinner than the second area, and the third area is thinner than the first area and is thinner than the second area.

Claims (40)

1. A method for forming a semiconductor device, the method comprising:

providing a semiconductor substrate;

forming a gate electrode over the semiconductor substrate having a first side and a second side; and

forming a gate dielectric under the gate electrode, wherein the gate dielectric has a first area under the gate electrode and adjacent the first side of the gate electrode; a second area under the gate electrode and adjacent the second side of the gate electrode; and a third area under the gate electrode that is between the first area and the second area; wherein the first area is thinner than the second area, and the third area is thinner than the first area and is thinner than the second area.

2. The method of claim 1 wherein the forming the gate dielectric under the gate electrode further comprises:

forming a first dielectric layer;

implanting an oxidation enhancing species into the semiconductor substrate to form oxidation enhancement regions; and

oxidizing the oxidation enhancement regions.

3. The method of claim 2 , wherein the implanting the oxidation enhancing species further comprises implanting the oxidation enhancing species into the gate electrode to form oxidation enhancement regions.

4. The method of claim 2 , wherein the implanting is performed at a tilt.

5. The method of claim 1 wherein the forming the gate dielectric under the gate electrode further comprises:

forming a first dielectric layer;

implanting an oxidation reduction species into the semiconductor substrate to form oxidation reducing regions; and

oxidizing the semiconductor substrate.

6. The method of claim 5 , wherein the implanting the oxidation enhancing species further comprises implanting the oxidation reduction species into the gate electrode to form oxidation reducing regions.

7. The method of claim 5 , wherein the implanting is performed at a tilt.

8. The method of claim 1 wherein the forming the gate dielectric under the gate electrode further comprises:

forming a first dielectric layer;

implanting an oxidation enhancing species into the semiconductor substrate to form oxidation enhancement regions;

implanting an oxidation reduction species into the semiconductor substrate to form oxidation reducing regions; and

oxidizing the semiconductor substrate, wherein oxidizing comprises forming a dielectric in the oxidation enhancement regions.

9. The method of claim 1 , further comprising:

forming a source extension region and a drain extension region after the forming the gate dielectric, wherein the source extension region is deeper than the drain extension region.

10. The method of claim 1 , further comprising:

forming a first spacer adjacent the first side of the gate electrode and a second spacer adjacent the second side of the gate electrode after the forming the gate dielectric.

11. A method for forming a semiconductor device, the method comprising:

providing a semiconductor substrate;

forming a dielectric layer over the semiconductor substrate;

forming a gate electrode over the dielectric layer, wherein the gate electrode has a first side and a second side opposite the first side;

implanting an oxidation enhancing species into the first side of the gate electrode and a first area of the semiconductor substrate, wherein the first area is under the gate electrode and adjacent the first side of the gate electrode; and

converting the first area to a first dielectric and a second area of the semiconductor substrate, wherein the second area is under the gate electrode and adjacent the second side of the gate electrode, to a second dielectric, wherein the thickness of the first dielectric is greater than the thickness of the second dielectric.

12. The method of claim 11 , wherein the converting comprises annealing the semiconductor substrate.

13. The method of claim 11 , wherein the implanting comprises implanting at least a species selected from the group consisting of germanium, oxygen, fluorine, and chlorine.

14. The method of claim 11 , further comprises implanting an oxidation reduction species into the second area.

15. The method of claim 14 , wherein the implanting the oxidation reduction species comprises implanting nitrogen.

16. The method of claim 11 , further comprising:

forming a source extension region and a drain extension region after the converting, the first area and the second area, wherein the source extension region is deeper than the drain extension region.

17. The method of claim 11 , further comprising:

forming a first spacer adjacent the first side of the gate electrode and a second spacer adjacent the second side of the gate electrode after the converting.

18. The method of claim 11 , wherein the implanting is performed at a tilt.

Assignments (23)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0670 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jul 11, 2008
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To: CITIBANK, N.A.
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SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2005
From: MATHEW, LEO; KOLAGUNTA, VENKAT R.; SING, DAVID C.
To: FREESCALE SEMICONDUCTOR, INC.
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