IP Library Granted Patent US 7,615,318
Granted Patent B2
US 7,615,318 · App. 11/253,061 · Granted Nov 10, 2009

Printing of design features using alternating PSM technology with double mask exposure strategy

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Quick Facts
Patent No.
US 7,615,318
App. No.
11/253,061
Granted
Nov 10, 2009
Kind
B2
Abstract

For cases where one edge of a design feature is to be printed through a shifter mask and another one is to be printed through a binary trim mask, and where no upsizing can be performed due to the local density of the design, it is proposed to add shifters with respect to the shifter mask in such a way that all the edges are printed by the phase shift mask.

Claims (31)

1. A method for printing design features within a photosensitive material using alternating Phase Shift Mask technology based on a double mask exposure strategy, comprising the steps of:

determining at least first, second and third design features adjacent one to the other, of which said first design feature has critical dimensions whereas said second and third design features do not have critical dimensions;

defining a phase shift mask and an associated binary trim mask, such that opposite edges of said first design feature are to be defined by the phase shift mask, that a first edge of said second design feature is to be defined by the phase shift mask while a second opposite edge thereof is to be defined by the binary trim mask, and that all edges of said third design feature are to be defined by the binary trim mask;

determining that said second design feature cannot be subject to an upsizing effect due to its proximity with said third design feature; and, as a result,

modifying the phase shift mask definition and the associated binary trim mask definition, so that said phase shift mask becomes suitable for defining said opposite edges of said first design feature along with said first and second opposite edges of said second design feature, and for defining one edge of said third design feature, whereas said binary trim mask becomes suitable for defining another opposite edge of said third design feature with upsizing thereof; and

fabricating the phase shift mask and the binary trim mask over a resist layer, in accordance with their respective definition thus modified, and lighting the resist layer through the phase shift mask and then through the binary trim mask.

2. The method according to claim 1 wherein the binary trim mask is designed to define dummy patterns as well, and wherein the localization of said dummy patterns takes into account, among other characteristics, the position and the dimensions of the upsized design features.

3. A method of fabricating a mask set comprising a phase shift mask and an associated binary trim mask, intended for printing design features within a photosensitive material using alternating Phase Shift Mask technology based on a double mask exposure strategy, comprising the steps of:

determining at least first, second and third design features adjacent one to the other, of which said first design feature has critical dimensions whereas said second and third design features do not have critical dimensions;

defining the phase shift mask and the binary trim mask, such that opposite edges of said first design feature are to be defined by the phase shift mask, that a first edge of said second design feature is to be defined by the phase shift mask while a second opposite edge thereof is to be defined by the binary trim mask, and that all edges of said third design features are to be defined by the binary trim mask;

determining that said second design feature cannot be subject to an upsizing effect due to its proximity with said third design feature; and, as a result,

modifying the phase shift mask definition and the associated binary trim mask definition, so that said phase shift mask become suitable for defining said opposite edges of said first design feature along with said first and second opposite edges of said second design feature, and for defining one edge of said third design feature, whereas said binary trim mask become suitable for defining another opposite edge of said third design feature with upsizing thereof; and

fabricating the phase shift mask and the binary trim mask in accordance with their respective definition thus modified.

4. The method according to claim 3 wherein the binary trim mask is designed to define dummy patterns as well, and wherein the localization of said dummy patterns takes into account, among other characteristics, the position and the dimensions of the upsized design features.

5. A method, comprising the steps of:

identifying first, second and third design features which are proximately located to one another, wherein the first design feature has critical dimensions, and the second and third design features do not have critical dimensions, but wherein at least a first portion of the second design feature cannot be subject to an upsizing effect due to its proximity to the third design feature; and

defining a phase shift mask and an associated binary trim mask, such that opposite edges of the first design feature along with certain opposite edges of the second design feature associated with the first portion not to be upsized and at least a portion of one edge of the third design feature are to be defined by the phase shift mask, and further such that remaining edges of the third design feature, including an edge opposite the portion of the one edge, along with edges of the second design feature associated with a second portion that may be subject to an upsizing effect are to be defined by the binary trim mask.

6. The method of claim 5 further comprising:

fabricating the phase shift mask and the binary trim mask over a resist layer; and

lighting the resist layer through the phase shift mask and then through the binary trim mask.

7. The method of claim 5 , further comprising:

identifying dummy patterns; and

defining the binary trim mask to include the dummy patterns as well.

8. The method of claim 7 , wherein a localization of the dummy patterns takes into account at least a position and dimensions of the design features which may be subject to an upsizing effect.

9. A method, comprising the steps of:

providing a phase shift mask for first, second and third design features which are proximately located to one another, the phase shift mask defining opposite edges of the first design feature, opposite edges of the second design feature located adjacent the first design feature, and a first edge of the third design feature located adjacent the second design feature;

providing an associated binary trim mask for the first, second and third design, the binary trim mask protecting the first, second and third design features, and the binary mask further defining a second edge of the third design feature which is opposite the first edge of the third design feature, wherein the second edge of the third design feature may be subject to an upsizing effect;

lighting a resist layer first through the phase shift mask and then through the binary trim mask.

10. The method of claim 9 wherein the opposite edges of the second design feature cannot be subject to an upsizing effect due to proximity of the second design feature to the first and third design features.

11. The method of claim 10 wherein the first edge of the third design feature cannot be subject to an upsizing effect due to proximity of the third design feature to the second design feature.

12. The method of claim 9 wherein the binary trim mask further defines dummy patterns whose position in the mask takes into account at least the position of the second edge of the third design feature which may be subject to an upsizing effect.

Assignments (28)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 1, 2006
From: PATTERSON, KYLE; RODY, IVES; COUDERC, CHRISTOPHE; MIRAMOND-COLLET, CORINNE
To: FREESCALE SEMICONDUCTOR INC.; STMICROELECTRONICS (CROLLES 2) SAS
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