Apparatus for optimizing diode conduction time during a deadtime interval
View Patent ↗Deadtime optimization techniques and circuits are provided which implement closed loop feedback to reduce a duration of a deadtime interval by reducing a diode conduction time (DCT) to an optimized or minimized value. Information regarding DCT is fed back to continuously adjust the relative delay between a first driver path which drives a first transistor and a second driver path which drives a second transistor. For instance, information regarding DCT can be measured and stored, and then used to generate a control signal which continuously adjusts (e.g., increases or decreases) a variable delay associated with a delay element in one of the driver paths of one of the transistors. The delay is adjusted to a value which drives the DCT towards an optimum value. By continuously changing the relative delay between the first driver path and the second driver path, the DCT can be driven to an optimum value.
1. A method, comprising:
providing a clock signal to a first delay element and a second delay element;
generating a first voltage (V 1 ) which includes a deadtime interval, wherein the deadtime interval comprises a pulse;
detecting the pulse during a first clock cycle, and measuring a duration of the pulse to generate a diode conduction time; and
generating a control signal based on the diode conduction time, wherein the control signal changes a relative delay between the first delay element and the second delay element to change the diode conduction time to an optimum non-zero value during a subsequent clock cycle after the first clock cycle.
2. A method according to claim 1 , wherein the step of providing a clock signal to a first delay element and a second delay element, comprises:
providing a clock signal to a first delay element to generate a first delayed clock signal and a second delay element to generate a second delayed clock signal.
3. A method according to claim 2 , further comprising the steps of:
driving a first transistor with the first delayed clock signal to generate a first output signal, wherein the first transistor turns off and stops conducting in response to the first delayed clock signal at a first time; and
driving a second transistor with the second delayed clock signal at a second time and turns on to begin conducting in response to the second delayed clock signal at the third time to generate a second output signal, wherein the second transistor has a parasitic diode associated therewith which conducts a current during a portion of the deadtime interval to cause the pulse in the first voltage (V 1 ) and wherein the second transistor begins conducting in response to the second delayed clock signal at a third time.
4. A method according to claim 3 , wherein the step of detecting the pulse ( 481 ), comprises:
comparing the first voltage (V 1 ) to a threshold voltage (Vthreshold), and
generating a diode conduction time output signal when the first voltage (V 1 ) is less than the threshold voltage (Vthreshold).
5. A method according to claim 3 , further comprising the step of:
storing the measured diode conduction time as a stored diode conduction time until the next clock cycle.
6. A method according to claim 3 , wherein the step of generating a first voltage (V 1 ) comprises:
combining the first output signal and the second output signal to generate the first voltage (V 1 ), wherein the first voltage (V 1 ) includes the deadtime interval, and wherein the deadtime interval occurs between the first time and the third time and comprises a pulse between the second time and the third time.
7. A method according to claim 5 , wherein the first delay element comprises a first fixed delay element which delays the first delayed clock signal by a fixed duration, and wherein the second delay element comprises a second variable delay element which delays the clock signal by a variable delay, and wherein the step of generating a control signal, comprises:
generating a control signal based on the stored diode conduction time during the first clock cycle, wherein the control signal changes the variable delay of the second variable delay element to change the relative delay between the first fixed delay element and the second variable delay element to change the diode conduction time to the optimum non-zero value during the next clock cycle after the first clock cycle.
8. A method according to claim 7 , wherein the step of generating a control signal, comprises:
generating a control signal based on the stored diode conduction time during the first clock cycle, wherein the control signal decreases the variable delay of the second variable delay element to decrease the diode conduction time during the next clock cycle.
9. A method according to claim 7 , wherein the step of generating a control signal, comprises:
generating a control signal based on the stored diode conduction time during the first clock cycle, wherein the control signal increases the variable delay of the second variable delay element to increase the diode conduction time during the next clock cycle.
10. An apparatus for reducing a deadtime interval in a first voltage (V 1 ) generated at a first node of the apparatus, comprising:
a clock which generates a clock signal;
a first delay element coupled to the clock and a second delay element coupled to the clock;
a first transistor which receives a first delayed clock signal from the first delay element and generates a first output signal;
a second transistor which receives a second delayed clock signal from the second delay element and generates a second output signal, wherein the first output signal is combined with the second output signal at a first node to generate a first voltage (V 1 ) which includes a deadtime interval, wherein a portion of the deadtime interval comprises a pulse; and
a control unit coupled between the first node and the second delay element, wherein the control unit is designed to detect, during a first clock cycle, the pulse; measure a duration of the pulse to generate a diode conduction time, and generate a control signal, based on the diode conduction time, which changes a relative delay between the first delay element and the second delay element.
11. An apparatus according to claim 10 , wherein the control signal changes the relative delay between the first delay element and the second delay element to change the diode conduction time during the next clock cycle after the first clock cycle.
12. An apparatus according to claim 10 , further comprising a driver circuit which comprises:
a first driver path comprising: the first delay element, wherein the first delay element is designed to generate the first delayed clock signal which is delayed by a fixed duration; and
a second driver path comprising: the second delay element, wherein the second delay element has a variable delay associated therewith and is designed to generate the second delayed clock signal which is delayed by a variable duration equal to the variable delay.
13. An apparatus according to claim 10 , wherein the first delay element comprises a first fixed delay element, and wherein the second delay element comprises a second variable delay element, and wherein the control signal adjusts the variable delay associated with the second variable delay element to change the relative delay between the first fixed delay element and the second variable delay element to change the diode conduction time to a optimum non-zero value during a next clock cycle after the first clock cycle.
14. An apparatus according to claim 10 , wherein the control unit comprises:
a diode conduction detector module designed to receive the first voltage (V 1 ) and a threshold voltage (Vthreshold), compare the first voltage (V 1 ) to the threshold voltage (Vthreshold), and generate a diode conduction time output signal when the first voltage (V 1 ) is less than the threshold voltage (Vthreshold).
15. An apparatus according to claim 11 , wherein the control signal changes the relative delay between the first delay element and the second delay element to change the diode conduction time to a optimum non-zero value during the next clock cycle after the first clock cycle.
16. An apparatus according to claim 12 , wherein the first transistor is coupled to the first delay element, the first node and a second node, and receives the first delayed clock signal at a gate of the first transistor, and turns off and stops conducting in response to the first delayed clock signal at a first time, and
wherein the second transistor is coupled to the second delay element, the first node and ground, and receives the second delayed clock signal at a gate of the second transistor at a second time, wherein the second transistor turns on and begins conducting in response to the second delayed clock signal at a third time, wherein the deadtime interval occurs between the first time and the third time, and
wherein the second transistor has a parasitic diode associated therewith which conducts a current for a portion of the deadtime interval between the second time and the third time to cause the pulse in the deadtime interval of the first voltage (V 1 ).
17. An apparatus according to claim 14 , wherein the first delay element comprises a first fixed delay element, and wherein the second delay element comprises a second variable delay element, and wherein the control unit further comprises:
a diode conduction measurement module designed to receive diode conduction time output signal, and measure the diode conduction time;
a storage element designed to store the measured diode conduction time as a stored diode conduction time until the next clock cycle; and
a delay adjustment module designed to use the stored diode conduction time during the next clock cycle to change the relative delay between the first fixed delay element and the second variable delay element to change the diode conduction time to the optimum non-zero value during the next clock cycle after the first clock cycle.
18. An apparatus according to claim 17 , wherein the delay adjustment module is designed to use the stored diode conduction time during the next clock cycle to adjust the variable delay associated with the second variable delay element to change the relative delay between the first fixed delay element and the second variable delay element to change the diode conduction time to the optimum non-zero value during the next clock cycle after the first clock cycle.
19. An apparatus according to claim 18 , wherein the delay adjustment module is designed to use the stored diode conduction time during the next clock cycle to decrease the relative delay between the first fixed delay element and the second variable delay element to decrease the second variable delay associated with the variable delay element to decrease the diode conduction time during the next clock cycle.
20. An apparatus according to claim 18 , wherein the delay adjustment module is designed to use the stored diode conduction time during the next clock cycle to increase the relative delay between the first fixed delay element and the second variable delay element to increase the variable delay associated with the second variable delay element to increase the diode conduction time during the next clock cycle.