Method and apparatus for mobility enhancement in a semiconductor device
View Patent ↗A method and apparatus is presented that provides mobility enhancement in the channel region of a transistor. In one embodiment, a channel region ( 18 ) is formed over a substrate that is bi-axially stressed. Source ( 30 ) and drain ( 32 ) regions are formed over the substrate. The source and drain regions provide an additional uni-axial stress to the bi-axially stressed channel region. The uni-axial stress and the bi-axial stress are both compressive for P-channel transistors and both tensile for N-channel transistors. The result is that carrier mobility is enhanced for both short channel and long channel transistors. Both transistor types can be included on the same integrated circuit.
1. A method for a transistor, comprising:
providing a substrate;
forming a channel region over the substrate that is bi-axially stressed; and
forming source and drain regions over the substrate, the source and drain regions providing a uni-axial stress to the channel region;
forming a first layer comprising silicon on the substrate, the first layer having a first intrinsic lattice constant; and
epitaxially growing a second layer on the first layer, the second layer comprising silicon and another element, the second layer having a second intrinsic lattice constant that is larger than the first intrinsic lattice constant.
2. The method of claim 1 , wherein the another element is germanium.
3. The method of claim 1 , wherein the transistor is a P-channel transistor.
4. The method of claim 1 , wherein both the bi-axial stress and the un-axial stress are compressive stress.
5. A method for a transistor, comprising:
providing a substrate;
forming a channel region over the substrate that is bi-axially stressed; and
forming source and drain regions over the substrate, the source and drain regions providing a uni-axial stress to the channel region;
forming a first layer comprising silicon on the substrate, the first layer having a first intrinsic lattice constant; and
epitaxially growing a second layer on the first layer, the second layer comprising silicon and another element, the second layer having a second intrinsic lattice constant that is smaller than the first intrinsic lattice constant.
6. The method of claim 5 , wherein the another element is carbon.
7. The method of claim 5 , wherein the transistor is an N-channel transistor.
8. The method of claim 5 , wherein forming a channel region further comprises:
forming a bi-axially stressed layer comprising silicon and germanium over the substrate;
forming a gate oxide over the bi-axially stressed layer; and
forming a gate over the gate oxide.
9. The method of claim 5 , wherein both the bi-axial stress and the uni-axial stress are tensile stress.
10. The method of claim 5 , wherein the substrate is a semiconductor substrate.
11. A method for forming a transistor, comprising:
providing a substrate;
forming a channel region over the substrate that is bi-axially stressed; and
forming source and drain regions over the substrate, the source and drain regions providing a uni-axial stress to the channel region;
forming a first layer comprising silicon over the substrate;
forming source and drain extensions in the first layer;
removing a predetermined amount of the first layer from the source and drain extensions to form source and drain recesses; and
epitaxially growing a first stressor in the source region and a second stressor in the drain region, the first and second stressors comprising silicon and germanium, the first and second stressors for providing the uni-axial stress to the channel region.
12. The method of claim 11 , wherein the channel region is bi-axially stressed along a plane of the transistor.
13. A method for forming a transistor, comprising:
providing a substrate;
forming a channel region over the substrate that is bi-axially stressed; and
forming source and drain regions over the substrate, the source and drain regions providing a uni-axial stress to the channel region;
wherein the channel region comprises silicon and germanium and the source and drain regions each comprise silicon and germanium, wherein a germanium content of the source and drain regions is higher than a germanium content of the channel region.
14. A method for forming a transistor, comprising:
providing a substrate;
forming a channel region over the substrate that is bi-axially stressed; and
forming source and drain regions over the substrate, the source and drain regions providing a uni-axial stress to the channel region;
wherein the channel region comprises silicon and carbon and the source and drain regions each comprise silicon and carbon, wherein a carbon content of the source and drain regions is higher than a carbon content of the channel region.