Low dropout voltage regulator using multi-gate transistors
View Patent ↗A voltage regulator includes a first multi-gate transistor, a differential stage, a second stage having a second multi-gate transistor, and a pass transistor to apply an output voltage and output current to a device load. Based on a feedback voltage associated with the output voltage, the differential stage modulates a bias voltage applied to a control electrode of the pass transistor. A first gate of the second multi-gate transistor generates a nominal bias current for the pass transistor, and the second gate adjusts the bias voltage based on an output of the differential stage so that transients in the regulator output voltage resulting from sudden changes in current drawn by the device load are reduced.
1. A low dropout (LDO) voltage regulator comprising:
a first multi-gate transistor having a first current electrode coupled to a first power supply voltage terminal, a first gate for receiving a reference signal, a second gate, and a second current electrode for providing a first current;
a differential stage having a first terminal coupled to said second current electrode of said first multi-gate transistor, and a second terminal coupled to a second power supply voltage terminal, for selectively diverting said first current in response to a difference between a reference voltage and a feedback voltage to provide a voltage on an output terminal thereof;
a second stage having an input terminal coupled to said output terminal of said differential stage, and an output terminal coupled to said second gate of said first multi-gate transistor; and
a pass transistor having a first current electrode for receiving an input voltage, and a second current electrode for providing an output voltage, and a control electrode coupled to said output terminal of said second stage.
2. The LDO voltage regulator of claim 1 , wherein said second stage comprises:
a second multi-gate transistor, having a first current electrode coupled to said first power supply voltage terminal, a first gate for receiving said reference signal, a second gate, and a second current electrode coupled to said second gate and to said output terminal of said second stage; and
a first transistor having a first current electrode coupled to said second current electrode of said second multi-gate transistor, a control electrode coupled to said output terminal of said differential stage, and a second current electrode coupled to said second power supply voltage terminal.
3. The LDO voltage regulator of claim 1 , wherein the first multi-gate transistor is a multiple independent gate field effect transistor (MIGFET).
4. The LDO voltage regulator of claim 3 , wherein the first multi-gate transistor is selected from the group consisting of a FinFET transistor, a floating gate metal oxide semiconductor (FGMOS) transistor, and a tri-gate transistor.
5. The LDO voltage regulator of claim 1 , further comprising a bias circuit comprising an output configured to generate the reference signal.
6. The LDO voltage regulator of claim 5 , wherein the bias circuit comprises:
a current source comprising a first terminal coupled to the first power supply voltage terminal and a second terminal;
a first transistor comprising a first current electrode coupled to the second terminal of the current source, a second current electrode coupled to the second power supply voltage terminal, and a control electrode coupled to the first current electrode;
a second transistor comprising a first current electrode, a second current electrode coupled to the second power supply voltage terminal, and a control electrode coupled to the control electrode of the first transistor; and
a third transistor comprising a first current electrode coupled to the first power supply voltage terminal, a second current electrode coupled to the first current electrode of the second transistor, and a control electrode coupled to the second current electrode, the second current electrode configured to generate the reference signal.
7. The LDO voltage regulator of claim 1 , further comprising:
a first resistor comprising a first terminal coupled to the second current electrode of the pass transistor and a second terminal configured to generate the feedback voltage; and
a second resistor comprising a first terminal coupled to the second terminal of the first resistor and a second terminal coupled to the second power supply voltage terminal.
8. The LDO voltage regulator of claim 1 , wherein the differential stage comprises:
a first transistor comprising a first current electrode coupled to the second current electrode of the first multi-gate transistor, a second current electrode, and a control electrode to receive the reference voltage;
a second transistor comprising a first current electrode coupled to the second current electrode of the first multi-gate transistor, a second current electrode, and a control electrode to receive the feedback voltage;
a third transistor comprising a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to the second power supply voltage terminal, and a control electrode coupled to the first current electrode; and
a fourth transistor comprising a first current electrode coupled to the second current electrode of the second transistor, a second current electrode coupled to the second power supply voltage terminal, and a control electrode coupled to the control electrode of the third transistor.
9. A low dropout (LDO) voltage regulator, comprising:
a pass transistor comprising a first current electrode coupled to a first power supply voltage terminal, a second current electrode configured to be coupled to a load, and a control electrode; and
a first multi-gate transistor, the first multi-gate transistor comprising a first current electrode coupled to the first power supply voltage terminal, a second current electrode configured to provide a bias voltage to the control electrode of the pass transistor, a first gate configured to receive a reference signal and a second gate coupled to the second current electrode.
10. The LDO voltage regulator of claim 9 , further comprising a second multi-gate transistor comprising a first current electrode coupled to the first power supply voltage terminal, a second current electrode, a first gate coupled to the first gate of the first multi-gate transistor, and a second gate coupled to the second gate of the first multi-gate transistor.
11. The LDO voltage regulator of claim 10 , further comprising a differential stage comprising a first terminal coupled to the second current electrode of the second multi-gate transistor, a second terminal configured to receive a reference voltage, and a third terminal coupled to receive a feedback voltage, the differential stage configured to divert a first current based on a difference between the feedback voltage and the reference voltage, the first current provided at the second current electrode of the second multi-gate transistor.
12. The LDO voltage regulator of claim 11 , wherein the differential stage further comprises:
a first transistor comprising a first current electrode coupled to the second current electrode of the second multi-gate transistor, a second current electrode, and a control electrode to receive the reference voltage;
a second transistor comprising a first current electrode coupled to the second current electrode of the second multi-gate transistor, a second current electrode, and a control electrode to receive the feedback voltage;
a third transistor comprising a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal, and a control electrode coupled to the first current electrode; and
a fourth transistor comprising a first current electrode coupled to the second current electrode of the second transistor, a second current electrode coupled to the second power supply voltage terminal, and a control electrode coupled to the control electrode of the third transistor.
13. The LDO voltage regulator of claim 12 , further comprising:
a fifth transistor comprising a first current electrode coupled to the second current electrode of the first multi-gate transistor, a second current electrode coupled to the second power supply voltage terminal, and a control electrode coupled to the second current electrode of the second transistor.
14. The LDO voltage regulator of claim 11 , further comprising:
a first resistor comprising a first terminal coupled to the second current electrode of the pass transistor and a second terminal coupled to the third terminal of the differential stage; and
a second resistor comprising a first terminal coupled to the second terminal of the first resistor and a second terminal coupled to a second power supply voltage terminal.
15. The LDO voltage regulator of claim 10 , further comprising a bias circuit comprising an output terminal configured to provide the reference signal.
16. The LDO voltage regulator of claim 15 , wherein the bias circuit comprises:
a current source comprising a first terminal coupled to the first power supply voltage terminal and a second terminal;
a first transistor comprising a first current electrode coupled to the second terminal of the current source, a second current electrode coupled to the second power supply voltage terminal, and a control electrode coupled to the first current electrode;
a second transistor comprising a first current electrode, a second current electrode coupled to a second power supply voltage terminal, and a control electrode coupled to the control electrode of the first transistor; and
a third transistor comprising a first current electrode coupled to the first power supply voltage terminal, a second current electrode coupled to the first current electrode of the second transistor, and a control electrode coupled to the second current electrode, the second current electrode configured to generate the reference signal.
17. A method of providing a regulated output voltage comprising:
receiving an input voltage at a first current electrode of a pass transistor;
modulating a conductivity of said pass transistor in response to a difference in voltage between a feedback voltage and a reference voltage to provide the regulated output voltage on a second current electrode of said pass transistor;
said modulating including generating a first current using a first gate of a first multi-gate transistor; and
changing a magnitude of said first current using a second gate of said first multi-gate transistor in response to detecting a change in load current.
18. The method of claim 17 , wherein changing a magnitude of the first current comprises increasing the first current in response to detecting an increase in load current.
19. The method of claim 17 , wherein generating the first current comprises generating the first current using a first gate of a second multi-gate transistor.
20. The method of claim 19 , wherein changing the magnitude of the first current comprises changing the magnitude using a second gate of the second multi-gate transistor.