Method for testing integrated circuit, and wafer
View Patent ↗A method for manufacturing an integrated circuit, a measurement apparatus of an integrated circuit, and a wafer that reduces damages inflicted on bonding pads while enabling a probe test to be accurately performed. A sensor cell is arranged on a wafer between chip formation regions. The sensor cell has a diaphragm. Sensor pads, connected to a doping region, are arranged on the surface of the diaphragm. Probe needles contact the sensor pads. This strains the doping region and produces a corresponding voltage measured by the probe needles connected to the sensor pads. Relative inclination angle and relative distance of a probe card, which includes the probe needles, and the wafer are determined based on the measured voltage. A conduction test is performed by having the probe needles contact the bonding pad of the wafer while maintaining the determined the relative position.
1. A method for testing an integrated circuit, formed on a chip and including a bonding pad, on a wafer, the method comprising:
arranging a sensor cell on the wafer;
pressing a probe needle against the sensor cell to measure a change in pressure with the sensor cell;
adjusting a relative position of the probe needle and the wafer based on the change in the pressure; and
conducting a probe test by having the probe needle contact the bonding pad at the relative position.
2. The method according to claim 1 , wherein the sensor cell is one of a plurality of sensor cells spread out on the wafer, and the relative position of the probe needle to the wafer is adjusted by adjusting at least one of relative inclination angle and relative distance of a probe card, which includes the probe needle, and the wafer.
3. The method according to claim 1 , wherein the sensor cell is arranged on the wafer outside a region in which the chip is formed.
4. A wafer including a plurality of chips, each chip having a bonding pad, the wafer comprising:
a sensor cell for measuring pressure applied by a probe needle that conducts a probe test by contacting a chip bonding pad.
5. The wafer of claim 4 , wherein the wafer includes a plurality of the sensor cells disposed on the wafer.
6. The wafer of claim 5 , wherein the wafer includes a plurality of scribe lines used during a cutting operation to separate the chips, wherein the sensor cells are located along the scribe lines.
7. The wafer of claim 5 , wherein there are more chips than sensor cells formed on the wafer.
8. The wafer of claim 4 , wherein the sensor cell comprises a Micro Electrical Mechanical System (MEMS) type device.
9. The wafer of claim 8 , wherein the sensor cell includes a diaphragm and a doping region formed near one end of an upper surface of the diaphragm.
10. The wafer of claim 9 , wherein impurities are injected into the doping region.
11. The wafer of claim 9 , wherein the doping region is substantially cross-shaped.
12. The wafer of claim 9 , wherein the sensor cell includes four sensor pads.
13. The wafer of claim 12 , wherein the four sensor pads include a first electrode pad for application of a power supply voltage (Vdd), a second electrode pad connected to ground, a positive electrode pad, and a negative electrode pad.