Nonvolatile storage array with continuous control gate employing hot carrier injection programming
View Patent ↗An array of storage cells include a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous storage elements (DSEs). A control gate overlies the first trench. The control gate may run perpendicular to the trenches and traverse the first and second trenches. In another implementation, the control gate runs parallel with the trenches. The storage cell may include one or more diffusion regions occupying an upper surface of the substrate between the first and second trenches. The diffusion region may reside between first and second control gates that are parallel to the trenches. Alternatively, a pair of diffusion regions may occur on either side of a control gate that is perpendicular to the trenches.
1. A method of programming a storage cell in an array of storage cells, comprising:
providing the array of storage cells, including a storage cell, the array comprising:
a semiconductor layer;
a first trench and a second trench spaced-apart from one another, wherein:
each of the first trench and the second trench extends from a surface of the semiconductor layer;
a portion of the semiconductor layer lies between the first and second trenches; and
the portion of the semiconductor layer has a first wall immediately adjacent to the first trench and a second wall immediately adjacent to the second trench;
a first control gate extending into the first trench;
a first source/drain region underlying the first trench;
a second source/drain region that:
lies within the portion of the semiconductor layer and adjacent to the surface of the semiconductor layer, wherein the second source/drain region is spaced apart from the first wall, the second wall, or both the first and second walls; or
underlies the second trench;
a first set of discontinuous storage elements lying between the first control gate and the first wall of the portion of the semiconductor layer; and
a second set of discontinuous storage elements lying between:
the first control gate; and
a part of the semiconductor layer at the surface of the portion of the semiconductor layer, wherein the part of the semiconductor layer lies outside the second source/drain region; and
biasing the first source/drain region to a drain programming voltage (V PD );
biasing the second source/drain region to 0 V; and
biasing the first control gate to a gate programming voltage (V PG ) to program a first bit of the storage cell by injecting charge into the first set of the discontinuous storage elements adjacent to the first wall of the portion of the semiconductor layer.
2. The method of claim 1 , further comprising biasing a semiconductor layer in which the first and second source/drain regions reside to 0 V.
3. The method of claim 1 , wherein:
providing the array of storage cells comprises providing the array of storage cells, wherein:
the second source/drain region underlies the second trench in the semiconductor layer;
the first control gate extends into the second trench; and
a third set of discontinuous storage elements lies between the first control gate and the second wall of the semiconductor layer; and
the method further comprises:
biasing the first source/drain region to 0 V:
biasing the second source/drain region to the V PD ; and
biasing the first control gate to the V PG to program a second bit of the second storage cell by injecting charge into the third set of the discontinuous storage elements.
4. The method of claim 3 , wherein biasing the first control gate comprises biasing a continuous control gate running perpendicular to the first and second trenches and traversing the first and second trenches.
5. The method of claim 2 , wherein:
providing the array of storage cells comprises providing the array of storage cells, wherein:
the second source/drain region lies within the portion of the semiconductor layer and adjacent to the surface of the semiconductor layer; and
a third set of discontinuous storage elements lies between the first control gate and the portion of the semiconductor layer and lies adjacent to the first wall and the surface of the portion of the semiconductor layer; and
the method further comprises:
biasing the first source/drain region to 0 V;
biasing the second source/drain region to the V PD ; and
biasing the first control gate to the V PG to program a second bit of the storage cell by injecting charge into the third set of the DSEs.
6. The method of claim 5 , wherein biasing the first control gate comprises biasing a continuous control gate overlying the first trench and running parallel to the first trench.
7. The method of claim 5 , wherein biasing the first control gate comprises biasing the first control gate running perpendicular to the first trench.
8. The method of claim 1 , further comprising:
biasing the portion of the semiconductor layer to a V EB ; and
biasing first control gate of the V PG to erase the first bit of the storage cell by removing charge from the first set of the discontinuous storage elements.
9. The method of claim 8 , further comprising floating the first source/drain region and the second source drain region when erasing the first bit of the storage cell.