Granted Patent B2

US 7,635,920 · App. 11/360,925 · Granted Dec 22, 2009

Abstract

Claims (30)

1. An integrated circuit, comprising:

a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit.

2. An integrated circuit as in claim 1 , further comprising:

a first device comprising a source and a drain, wherein the source of the first device comprises a first implant; and

a second device comprising a source and a drain, wherein the source of the second device comprises a second implant,

wherein a first implant direction used to form the first implant is different than a second implant direction used to form the second implant.

3. An integrated circuit as in claim 1 , wherein the non-visually discernable characteristic comprises an implant direction of an implant.

4. An integrated circuit as in claim 3 , wherein the implant comprises a halo implant.

5. An integrated circuit as in claim 1 , wherein the non-visually discernable characteristic comprises a crystal lattice orientation.

6. An integrated circuit as in claim 1 , wherein the non-visually discernable characteristic is discerned during manufacture of the integrated circuit.

7. An integrated circuit as in claim 1 , wherein the visually discernable indicator comprises:

a first portion used during design of the integrated circuit; and

a second portion used during manufacture of the integrated circuit.

8. An integrated circuit as in claim 7 , wherein the first portion of the visually discernable indicator is used during a design rule verification process.

9. An integrated circuit as in claim 7 , wherein the second portion of the visually discernable indicator comprises a function indicator and a direction indicator.

10. An integrated circuit of claim 1 , wherein the visually discernable indicator is formed in an IP block.

11. An integrated circuit of claim 1 , wherein the visually discernable indicator is formed using a mask while forming the integrated circuit.

12. An integrated circuit formed using at least one implant, the integrated circuit comprising:

a visually discernable indicator which indicates a direction of the at least one implant from visual inspection.

13. An integrated circuit as in claim 12 , wherein the at least one implant comprises a halo implant for a source region.

14. An integrated circuit as in claim 12 , wherein the visually discernable indicator comprises: a first portion used during design of the integrated circuit; and a second portion used during manufacture of the integrated circuit.

15. An integrated circuit as in claim 14 , wherein the second portion of the visually discernable indicator comprises a function indicator and a direction indicator.

16. An integrated circuit of claim 12 , wherein the visually discernable indicator is formed in an IP block.

17. An integrated circuit of claim 16 , wherein the visually discernable indicator is formed using a mask while forming the integrated circuit.

18. An integrated circuit, comprising:

at least one indicator to indicate an implant direction of a source halo implant; and

an asymmetrically doped device comprising a source region and a drain region, wherein the source region comprises a source halo implant region, and

wherein the source halo implant region of the asymmetrically doped device has a higher dopant concentration than a region adjacent the drain region, wherein the region adjacent the drain region has a same conductivity type as the source halo implant region.

19. An integrated circuit of claim 18 , wherein the at least one indicator is formed in an P block.

20. An integrated circuit of claim 18 , wherein the at least one indicator is formed using a mask while forming the integrated circuit.

Assignments (18)