Gate dielectric and metal gate integration
View Patent ↗A CMOS device is provided which comprises (a) a substrate ( 103 ); (b) a gate dielectric layer ( 107 ) disposed on the substrate, the gate dielectric comprising a metal oxide; (c) an NMOS electrode ( 105 ) disposed on a first region of said gate dielectric; and (d) a PMOS electrode ( 115 ) disposed on a second region of said gate dielectric, the PMOS electrode comprising a conductive metal oxide; wherein the surface of said second region of said gate dielectric comprises a material selected from the group consisting of metal oxynitrides and metal silicon-oxynitrides.
1. A method for making a semiconductor device, comprising:
providing a semiconductor substrate;
forming a high-k dielectric layer on the substrate, the high-k dielectric layer having first and second regions;
forming an NMOS layer stack on the high-k dielectric layer in the first region, and then subjecting the high-k dielectric layer to nitridation within the second region; and
forming a PMOS layer stack within the second region.
2. The method of claim 1 wherein, prior to the nitridation step, the NMOS layer stack is formed over the first and second regions of the device and is subjected to masking and etching steps to remove it from the second region of the device.
3. The method of claim 1 wherein, after the nitridation step, the PMOS layer stack is formed over the first and second regions of the device and is subjected to masking and etching steps to remove it from the first region of the device.
4. The method of claim 1 wherein, prior to the nitridation step, a hard mask is formed over the first region of the device.
5. The method of claim 4 , wherein the hard mask is removed after the nitridation step and before the step of forming the PMOS layer stack.
6. The method of claim 1 , wherein the high-k dielectric layer comprises a metal oxide.
7. The method of claim 1 , wherein the high-k dielectric layer comprises HfO 2 .
8. The method of claim 1 , wherein the NMOS layer stack comprises a layer of TaC.
9. The method of claim 8 , wherein the NMOS layer stack further comprises a layer of a material selected from the group consisting of TaSiN and TiN.
10. The method of claim 1 , wherein the PMOS layer stack comprises a conductive metal oxide.
11. The method of claim 10 , wherein the PMOS layer stack comprises an iridium oxide.
12. The method of claim 1 , further comprising the step of forming a diffusion barrier layer between the substrate and the high-k dielectric layer.
13. The method of claim 1 , wherein the step of subjecting the high-k dielectric layer to nitridation within the second region involves use of a Modified Magnetron Typed (MMT) plasma reactor.
14. The method of claim 13 , wherein the MMT plasma reactor is provided with a nitrogen-containing atmosphere.
15. The method of claim 14 , wherein the nitrogen-containing atmosphere comprises a gas selected from the group consisting of ammonia and oxides of nitrogen.
16. The method of claim 1 , wherein the step of subjecting the high-k dielectric layer to nitridation within the second region involves a thermal anneal in a nitrogen-containing atmosphere.
17. The method of claim 16 , wherein the nitrogen-containing atmosphere comprises a gas selected from the group consisting of ammonia and oxides of nitrogen.