IP Library Granted Patent US 9,065,475
Granted Patent B2
US 9,065,475 · App. 12/302,221 · Granted Jun 23, 2015

Sin-Cos sensor arrangement, integrated circuit and method therefor

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,065,475
App. No.
12/302,221
Granted
Jun 23, 2015
Kind
B2
Abstract

A Sin-Cos sensor arrangement comprises a Sin-Cos sensor operably coupled to signal processing logic via a hardware interface. The hardware interface is arranged to provide the signal processing logic with analog sine and cosine waveforms indicative of fine position data and binary counterparts of the analog sine and cosine waveforms (Phase_A and Phase_B) indicative of rough position data. The signal processing logic is arranged to determine a position and speed of the Sin-Cos sensor by compensating for inaccuracies between analog sine and cosine waveforms and their binary counterparts. In this manner, a fully software-based solution provides a fast, efficient and high accuracy position and speed estimation based on the processing of the analog sine and cosine signals and the digital representation thereof of the Sin-Cos sensor.

Claims (73)

1. A Sin-Cos sensor arrangement comprising:

signal processing logic;

a Sin-Cos sensor operably coupled to the signal processing logic via a hardware interface, wherein the hardware interface is arranged to provide the signal processing logic with analogue sine and cosine waveforms indicative of fine position data and binary counterparts of the analogue sine and cosine waveforms (phase_A and phase_B) indicative of rough position data, wherein the signal processing logic is arranged to determine a position and speed of the Sin-Cos sensor by compensating for inaccuracies between the analogue sine and cosine waveforms and the binary counterparts.

2. The Sin-Cos sensor arrangement of claim 1 wherein the signal processing logic comprises a software driver to perform compensation for the inaccuracies between the analogue sine and cosine waveforms and the binary counterparts.

3. The Sin-Cos sensor arrangement of claim 1 wherein the signal processing logic comprises angle extractor logic arranged to provide the fine position data (θ low ) based on one or more of the following:

analysis performed on the analogue sine and cosine waveforms, analysis of the analogue sine and cosine waveforms or non-linear waveforms, for example where the non-linear waveforms are approximated either by a set of differential functions and/or using a look-up table.

4. The Sin-Cos sensor arrangement of claim 1 wherein the analogue sine and cosine waveforms are generated by either the hardware interface or directly by the Sin-Cos sensor.

5. The Sin-Cos sensor arrangement of claim 1 wherein the signal processing logic comprises digital position extractor logic arranged to provide the rough position data (θ high ) based on phase counting of the binary counterparts (phase_A and phase_B).

6. The Sin-Cos sensor arrangement of claim 5 wherein angle extractor logic and the digital position extractor logic are operably coupled to position composer logic arranged to combine the fine position data (θ low ) with rough position data (θ high ).

7. The Sin-Cos sensor arrangement of claim 6 , wherein the position composer logic is operably coupled to angle tracking observer logic arranged to provide a smooth composed position (θ est ).

8. The Sin-Cos sensor arrangement of claim 6 wherein the position composer logic is operably coupled to angle tracking observer logic arranged to provide speed estimates (ω est ).

9. The Sin-Cos sensor arrangement of claim 6 , wherein the angle tracking observer logic applies a transfer function to provide a smooth composed position (θ est ):

F

(

s

)

=

Θ

^

(

s

)

Θ

(

s

)

=

K

1

(

1

+

K

2

s

)

s

2

+

K

1

K

2

s

+

K

1

;

wherein {circumflex over (Θ)}(s) is a position at a first time, Θ(s) is a position at a second time, K 1 is a first parameter of the angle tracking observer, K 2 is a second parameter of the angle tracking observer, and s is a time variable.

10. The Sin-Cos sensor arrangement of claim 2 , wherein the software driver is operably coupled to a digital signal controller or microcontroller arranged to utilise Sin-Cos output signals.

11. An integrated circuit for operable coupling to a Sin-Cos sensor, comprising:

signal processing logic operably coupled to a hardware interface, wherein the hardware interface is arranged to provide the signal processing logic with analogue sine and cosine waveforms indicative of fine position data and binary counterparts of the analogue sine and cosine waveforms (phase_A and phase_B) indicative of rough position data, wherein the signal processing logic is arranged to determine a position and speed of the Sin-Cos sensor by compensating for inaccuracies between the analogue sine and cosine waveforms and the binary counterparts.

12. The integrated circuit of claim 11 wherein the signal processing logic comprises a software driver to perform compensation for the inaccuracies between the analogue sine and cosine waveforms and the binary counterparts.

13. The integrated circuit of claim 11 wherein the signal processing logic comprises angle extractor logic arranged to provide the fine position data (θ low ) based on one or more of the following:

analysis performed on the analogue sine and cosine waveforms, analysis of the analogue sine and cosine waveforms or non-linear waveforms, for example where the non-linear waveforms are approximated either by a set of differential functions and/or using a look-up table.

14. The integrated circuit of claim 11 wherein the analogue sine and cosine waveforms are generated by either the hardware interface or directly by the Sin-Cos sensor.

15. The integrated circuit of claim 11 , wherein the signal processing logic comprises digital position extractor logic arranged to provide the rough position data (θ high ) based on phase counting of the binary counterparts (Phase_A and Phase_B).

16. The integrated circuit of claim 15 wherein angle extractor logic and the digital position extractor logic are operably coupled to position composer logic arranged to combine the fine position data (θ low ) with the rough position data (θ high ).

17. The integrated circuit of claim 16 , wherein the position composer logic is operably coupled to angle tracking observer logic arranged to provide a smooth composed position (θ est ).

18. The integrated circuit of claim 16 wherein the position composer logic is operably coupled to angle tracking observer logic arranged to provide speed estimates (ω est ).

19. The integrated circuit of claim 12 the software driver is operably coupled to a digital signal controller or microcontroller arranged to utilise Sin-Cos output signals.

20. A method for determining a position and speed of a Sin-Cos sensor comprising:

sampling, by a hardware interface, analogue sine and analogue cosine signals indicative of fine position data (θ low );

performing phase decoding of the sampled analogue sine and analogue cosine signals to generate binary counterpart signals indicative of rough position data (θ high ); and

combining, by a signal processing logic, the rough position data (θ high ) with the fine position data (θ low ) to compensate for inaccuracies between the analogue sine and cosine waveforms and the binary counterpart signals thereby determining the position and speed of the Sin-Cos sensor.

21. The method for determining the position and speed of the Sin-Cos sensor of claim 20 wherein the step of combining comprises placing the rough position data in higher bits; and adding the higher bits to the fine position data.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0807 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →