Method of tiling analog circuits
View Patent ↗The present invention provides a method for tiling an integrated circuit having a critically matched device such as a transistor. The method obtains an advantage of automatically improving metallic density over critically matched devices thus yielding improved CMP. The method may include the steps of: identifying critically matched devices in the integrated circuit; placing metal tiles over the critically matched device; performing a density test around each critically matched device; and if a density test is not satisfied around a critically matched device, placing at least one metal strip over a critically matched device.
1. A method for placing tiles in an integrated circuit having critically matched devices, the method comprising the steps of:
identifying critically matched devices in the integrated circuit;
calculating a metal spacing for tiles in the integrated circuit;
calculating a lateral spacing for tiles in the integrated circuit;
placing tiles around the critically matched devices based on the metal spacing and the lateral spacing;
performing a density test over each critically matched device; and
if a density test is not satisfied over a critically matched device, placing at least one metal strip over a transistor;
wherein the transistor includes a gate and wherein the metal strip is substantially the same length as the transistor gate.
2. The method according to claim 1 , wherein the integrated circuit has more than one layer and wherein the step of placing at least one metal strip further comprises placing a metal strip in each layer of the integrated circuit above the critically matched device.
3. The method according to claim 1 , wherein the transistor includes an area of symmetry and the method further comprising placing at least one metal strip over a transistor such that the metal strip substantially overlies an area of symmetry of the transistor.
4. The method according to claim 1 , wherein the step of performing a density test over each critically matched device further comprises measuring metallic density in sequential areas of the integrated circuit.
5. The method according to claim 4 further comprising comparing metallic density in an area of the integrated circuit to a minimum and a maximum.
6. A method for placing tiles in an integrated circuit having critically matched devices, the method comprising the steps of:
identifying critically matched devices in the integrated circuit;
calculating a metal spacing for tiles in the integrated circuit;
calculating a lateral spacing for tiles in the integrated circuit;
placing tiles around the critically matched devices based on the metal spacing and the lateral spacing;
performing a density test over each critically matched device; and if a density test is not satisfied over a critically matched device, placing at least one metal strip over a transistor;
wherein the transistor includes a source or drain and wherein the metal strip is substantially the same width as the transistor source or drain.
7. A method for placing tiles in an integrated circuit having critically matched devices, the method comprising the steps of:
identifying critically matched devices in the integrated circuit;
calculating a metal spacing for tiles in the integrated circuit;
calculating a lateral spacing for tiles in the integrated circuit;
placing tiles around the critically matched devices based on the metal spacing and the lateral spacing;
performing a density test over each critically matched device; and
if a density test is not satisfied over a critically matched device, placing a metal strip over a transistor having a first gate and a second gate such that the metal strip is substantially symmetrically positioned with respect to the first gate and the second gate.