MOS devices with multi-layer gate stack
View Patent ↗An embodiment of a semiconductor device includes a semiconductor substrate having a principal surface, spaced-apart source and drain regions separated by a channel region at the principal surface, and a multilayered gate structure located over the channel region. The multilayered gate structure includes a gate dielectric layer in contact with the channel region, a first conductor comprising a metal oxide overlying the gate dielectric layer, a second conductor overlying the first conductor, and an impurity migration inhibiting layer between the gate dielectric layer and the first conductor or between the first conductor and the second conductor.
1. A semiconductor device, comprising:
a semiconductor substrate having a principal surface;
spaced-apart source and drain regions separated by a channel region at the principal surface;
a multilayered gate structure located over the channel region, wherein the multilayered gate structure comprises:
a gate dielectric layer having an interface in contact with the channel region;
a plurality of stacked combination layers sequentially arranged and overlying the gate dielectric layer, wherein each of the combination layers comprises:
a first conductor comprising a metal oxide, and
an impurity migration inhibiting layer comprising a conductive absorption material overlying or underlying the first conductor, and having a higher affinity for oxygen than the first conductor for reducing migration of the mobile species toward the interface; and
a second conductor overlying the plurality of stacked combination layers.
2. The device of claim 1 , wherein the impurity migration inhibiting layer and the first conductor comprise the same metal element.
3. The device of claim 1 , wherein the gate dielectric layer comprises oxides of Hf, Zr or HfZr.
4. A semiconductor device, comprising:
a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate;
a multilayered gate structure located above the channel region and having one or more regions containing a mobile impurity, wherein the gate structure comprises:
a gate oxide having an interface in substantial contact with the channel region;
a plurality of layers of metal oxide overlying the gate oxide;
a plurality of impurity migration inhibiting layers, each comprising a conductive absorption material and having a higher affinity for oxygen than the plurality of layers of metal oxide for reducing migration of the mobile species toward the interface, wherein the plurality of impurity migration inhibiting layers are formed overlying the gate oxide and in an alternating arrangement with the plurality of layers of metal oxide; and
a second conductor overlying the plurality of layers of metal oxide and the plurality of impurity absorption layers.
5. The device of claim 4 , wherein a topmost one of the plurality of impurity migration inhibiting layers is located between a topmost one of the plurality of layers of metal oxide and the second conductor.
6. The device of claim 4 , wherein a topmost one of the plurality of layers of metal oxide is located between a topmost one of the plurality of impurity migration inhibiting layers and the gate oxide.
7. The device of claim 4 , wherein the plurality of layers of metal oxide and the plurality of impurity migration inhibiting layers are arranged in pairs, so that for each pair, a layer of metal oxide is closer to the gate oxide and an impurity migration inhibiting layer is closer to the second conductor.
8. The device of claim 4 , wherein the plurality of layers of metal oxide and the plurality of impurity migration inhibiting layers are arranged in pairs, so that for each pair, an impurity migration inhibiting layer is closer to the gate oxide and a layer of metal oxide is closer to the second conductor.
9. The device of claim 4 , wherein the MOS device is a PMOS device and the layers of metal oxide comprise an oxide of MoSi and the impurity migration inhibiting layers comprise MoSi.
10. A semiconductor device, comprising:
a semiconductor substrate having a principal surface;
spaced-apart source and drain regions separated by a channel region at the principal surface;
a multilayered gate structure located over the channel region, wherein the multilayered gate structure comprises:
a gate oxide layer having an interface in contact with the principal surface;
a first combination of layers overlying the gate oxide layer, which comprises:
a first conductor layer comprising a metal oxide, and
a first absorption layer of a conductive absorption material formed in contact with and overlying or underlying the first conductor layer, and having a higher affinity for oxygen than the first conductor layer for reducing migration of the mobile species toward the interface;
a second combination of layers, overlying the first combination of layers, which comprises:
a second conductor layer comprising the metal oxide, and
a second absorption layer comprising the conductive absorption material that is formed in contact with and overlying or underlying the second conductor layer, and in a same relative arrangement as the first conductor layer and the first absorption layer; and
a third conductor layer overlying the second combination of layers.
11. The device of claim 10 , wherein the first and second conductor layers comprise molybdenum-silicon-oxide, the third conductor layer comprises a polycrystalline semiconductor and the first and second absorption layers comprise molybdenum-silicide.
12. The device of claim 10 , wherein the gate oxide layer comprises oxides of Hf, Zr or HfZr.
13. The device of claim 10 , wherein the first conductor layer comprises one or more silicates of Mo, Nb, V, Re, Ru, Os, Rh, Ir, Pd, or nitrides of such silicates.
14. The device of claim 10 , wherein the first absorption layer comprises at least one metallic element in common with the first conductor layer.
15. The device of claim 10 , wherein the semiconductor device is a PMOS device and the first conductor layer comprises an oxide of MoSi and the first absorption layer comprises MoSi.
16. The device of claim 10 , wherein the third conductor layer comprises a polycrystalline semiconductor, the absorption layer comprises molybdenum-silicide, the gate oxide layer comprises oxides of Hf, Zr or HfZr, and the first conductor layer comprises one or more silicates of Mo, Nb, V, Re, Ru, Os, Rh, Ir, Pd, or nitrides of such silicates.