Electronic device, integrated circuit and method for selecting of an optimal sampling clock phase
View Patent ↗An electronic device comprises a number of sub-systems coupled via an interface. One of the number of sub-systems comprises logic for receiving a frame of input data having a plurality of phases on respective data paths. The electronic device further comprises logic for performing cross correlation on the received input data with a pre-determined bit pattern, operably coupled to selection logic, for selecting a single phase from the plurality of phases sent to the interface to sample the received input data in a middle region of a data bit period in response to the cross correlation.
1. An electronic device, comprises:
a number of sub-systems coupled via an interface, wherein one of the number of sub-systems comprises logic for receiving a frame of input data having a plurality of phases on respective data paths;
logic for performing cross correlation on the received input data with a pre-determined bit pattern, operably coupled to selection logic, for selecting a single phase from the plurality of phases either sent to or generated by the interface to sample the received input data in a middle region of a data bit period in response to the cross correlation and disable at least one data path comprising at least one unselected phase from the plurality of phases, wherein in response to determining there is no phase of a respective data path that matches a cross-correlation threshold in a first sampling time period, the logic for performing cross correlation performs cross correlation over a subsequent sampling time period.
2. An integrated circuit comprising:
at least one of a number of sub-systems, wherein the integrated circuit comprises logic for receiving a frame of input data having a plurality of phases on respective data paths;
logic for performing cross correlation on the received input data with a pre-determined bit pattern, operably coupled to selection logic, for selecting a single phase from the plurality of phases either sent to or generated by the interface to sample the received input data in a middle region of a data bit period in response to the cross correlation and disable at least one data path comprising at least one unselected phase from the plurality of phases and disable at least one data path comprising at least one unselected phase from the plurality of phases, wherein in response to determining there is not phase of a respective data path that matches a cross-correlation threshold in a first sampling time period, the logic for performing cross correlation performs cross correlation over a subsequent sampling time period.
3. The integrated circuit of claim 2 wherein the integrated circuit is a radio frequency integrated circuit or a baseband integrated circuit.
4. The integrated circuit of claim 3 wherein the cross-correlation logic, is operably coupled to sampling logic, and arranged to select a single phase to be used by the sampling logic by determining whether cross correlating the input data with a pre-determined bit pattern matches or exceeds a cross-correlation threshold.
5. The integrated circuit of claim 2 wherein the cross-correlation logic, is operably coupled to sampling logic, and arranged to select a single phase to be used by the sampling logic by determining whether cross correlating the input data with a pre-determined bit pattern matches or exceeds a cross-correlation threshold.
6. The integrated circuit of claim 2 wherein detection logic operably coupled to the logic for performing cross correlation and arranged to detect a start of a frame of received input data to initiate a sample selection process.
7. The integrated circuit of claim 2 wherein the logic for performing cross correlation on the plurality of phases on respective data paths performs cross correlation over one or two sampling time periods.
8. The integrated circuit of claim 2 wherein in response to determining there is no phase of a respective data path that matches or exceeds a cross-correlation threshold in a subsequent sampling time period, the logic for performing cross correlation performs a final cross-correlation match by taking a highest cross-correlation data path match from the cross correlation performed in the first sampling time period.
9. The integrated circuit of claim 8 wherein the logic for cross correlation adding a lowest cross-correlation match from the first sampling time period to the final cross-correlation match.
10. The integrated circuit of claim 9 wherein divide-by-‘x’ logic, for example divide-by-two logic, operably coupled to the logic for performing cross correlation to provide to the selection logic a value substantially in a middle range between a lowest correlation data path and a highest correlation data path recorded over the first and second sampling time periods to place the sample in the middle of an incoming data bit period.
11. The integrated circuit of claim 10 wherein capping logic operably coupled to the divide-by-‘x’ logic and arranged to provide at least one of a high cap and a low cap on a value supplied to the selection logic.
12. The integrated circuit of claim 10 wherein a value for ‘x’ in the divide-by-‘x’ logic positions the sample to a left or right of the middle region of the incoming data bit period.
13. The integrated circuit of claim 10 wherein the divide-by-‘x’ logic is arranged to divide by a fractional value.
14. The integrated circuit of claim 2 wherein in response to determining there is a phase of a respective data path that matches or exceeds the cross-correlation threshold in the subsequent sampling time period, a highest cross-correlation data path match is stored from the subsequent sampling time period.
15. The integrated circuit of claim 14 wherein in response to determining that there is a phase of a respective data path that matches or exceeds the cross-correlation threshold in the subsequent sampling time period, the logic for performing cross correlation performs a final cross-correlation match by taking a highest cross-correlation match in the subsequent sampling time period plus a number of selection phases.
16. The integrated circuit of claim 2 wherein the selection logic selects the single phase to sample the received input data for:
(i) the current frame only, or
(ii) until a start of subsequent frame where a synchronisation pattern is identified.
17. The integrated circuit of claim 2 wherein a delay element operably coupled to the logic for performing cross correlation and arranged to provide a delay equivalent to a number of data bit periods it took to make a decision on a correct clock phase and perform a data path selection.
18. The integrated circuit of claim 2 wherein the integrated circuit is arranged to support third generation or fourth generation communication.
19. A method for sampling received input data in an electronic device comprising a number of sub-systems coupled via an interface, the method comprising:
receiving a frame of input data comprising an input data bit and having a plurality of phases on respective data paths;
performing cross correlation on the received input data with a pre-determined bit pattern;
selecting a single phase from the plurality of phases either sent to or generated by the interface to sample the received input data in a middle region of a data bit period in response to the cross correlation; and
disabling at least one data path comprising at least one unselected phase from the plurality of phases; and
disabling at least one data path comprising at least one unselected phase from the plurality of phases; and
in response to determining there is no phase of a respective data path that matches a cross-correlation threshold in a first sampling time period, performing cross correlation over a subsequent sampling time period.