Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode
View Patent ↗A semiconductor fabrication process includes forming first and second transistors over first and second well regions, respectively where the first transistor has a first gate dielectric and the second transistor has a second gate dielectric different from the first gate dielectric. The first transistor has a first gate electrode and the second transistor has a second gate electrode. The first and second gate electrodes are the same in composition. The first gate dielectric and the second gate dielectric may both include high-K dielectrics such as Hafnium oxide and Aluminum oxide. The first and second gate electrodes both include a gate electrode layer overlying the respective gate dielectrics. The gate electrode layer is preferably either TaSiN and TaC. The first and second gate electrodes may both include a conductive layer overlying the gate electrode layer. In one such embodiment, the conductive layer may include polysilicon and tungsten.
1. A semiconductor fabrication process, comprising:
forming a first gate dielectric over and in contact with a well region and a second gate dielectric over and in contact with a second well region wherein the compositions of the first and second gate dielectric are different; and
forming a first gate electrode over and in contact with the first gate dielectric and a second gate electrode over and in contact with the second gate dielectric wherein the first and second gate electrodes are equivalent in composition and thickness;
wherein the first gate dielectric includes a second dielectric film overlying a first dielectric film on an upper surface of the first well region and wherein the second gate dielectric includes a third dielectric film overlying the first dielectric film on the upper surface of the second well region.
2. The process of claim 1 , wherein the first and second gate dielectrics are both high-K dielectrics.
3. The process of claim 2 , wherein the first gate dielectric is Lanthanum oxide and the second gate dielectric is Aluminum oxide.
4. The process of claim 3 , wherein the first and second gate electrodes include a tantalum-bearing layer over and in contact with the first and second dielectrics respectively.
5. The process of claim 4 , wherein the tantalum bearing layer consists substantially of TaC.
6. The process of claim 4 , wherein the tantalum bearing layer consists substantially of TaSiN.
7. The process of claim 4 , wherein the first and second gate electrodes include a conductive layer over and in contact with the tantalum bearing layer, wherein the conductive layer is selected from the group consisting of polysilicon and tungsten.
8. A semiconductor process, comprising:
forming a first transistor over a first well region and a second transistor over a second well region;
the first transistor having a first gate dielectric and the second transistor having a second gate dielectric different in composition from the first gate dielectric;
the first transistor having a first gate electrode and the second transistor having a second gate electrode, wherein the first and second gate electrodes are the same in composition; and
wherein the first gate dielectric and the second gate dielectric are both high-K dielectrics.
9. The process of claim 8 , wherein the first gate dielectric is Hafnium oxide and the second gate dielectric is Aluminum oxide.
10. The process of claim 9 , wherein the first second gate electrodes both include a gate electrode layer above and in contact with the respective gate dielectrics, wherein the gate electrode layer is selected from a group consisting of TaSiN and TaC.
11. The process of claim 10 , wherein the first and second gate electrodes both include a conductive layer over the corresponding gate electrode layer, wherein the conductive layer is selected from the group consisting of polysilicon and tungsten.
12. An integrated circuit, comprising:
a first transistor formed overlying a first well region of a semiconductor substrate, wherein the first transistor includes a first gate electrode overlying a first metal-oxide gate dielectric;
a second transistor formed overlying a second wall region of the semiconductor substrate, wherein the second transistor includes a second gate electrode overlying a second metal-oxide gate dielectric;
wherein the first and second gate dielectrics differ in composition and further wherein the first and second gate electrodes are substantially equivalent in composition and thickness.
13. The integrated circuit of claim 12 , wherein the first and second gate dielectric are high-K dielectrics.
14. The integrated circuit of claim 13 , wherein the first and second gate electrodes include a conductive layer of a material selected from polysilicon and tungsten overlying a gate electrode layer comprised of a material selected from TaSiN and TaC.
15. The integrated circuit of claim 14 , wherein the first gate dielectric is comprised of Lanthanum oxide and the second gate dielectric is comprised of Aluminum oxide.
16. The integrated circuit of claim 12 , wherein the first gate dielectric includes a second gate dielectric film overlying a first dielectric film.
17. The integrated circuit of claim 16 , wherein the second gate dielectric includes a third gate dielectric film overlying the first dielectric film.
18. The integrated circuit of claim 17 , wherein the first dielectric film is comprised of a material selected form SiO 2 and Hafnium oxide, the second dielectric film is comprised of Lanthanum oxide, and the third dielectric film is comprised of Aluminum oxide.
19. The integrated circuit of claim 18 , wherein the first dielectric film a material selected from Hafnium oxide, Aluminum oxide, and SiO 2 and the second dielectric film is Lanthanum oxide.
20. The integrated circuit of claim 16 , wherein the second gate dielectric consists of the second dielectric film overlying the second well region.
21. A method for forming over a semiconductor substrate a first gate stack in a first gate location for a transistor of a first conductivity type and a second gate stack in a second gate location for a transistor of the second conductivity, comprising:
forming a first gate dielectric layer over the first gate location and the second gate location, wherein the first gate dielectric layer comprises a first high-k dielectric;
removing the first gate dielectric layer in an area over the second gate location;
forming a second gate dielectric over the first gate location and the second gate location, wherein the second gate dielectric layer comprises a second high-k dielectric different from the first high-k dielectric;
removing the second gate dielectric in an area over the first gate location;
forming a first gate layer over the first gate location and the second gate location;
removing a first portion of the gate layer to leave a second portion of the first gate layer over the first gate location; and
forming a second gate layer over the first gate location and the second gate location;
wherein the removing the first gate dielectric layer occurs before the forming the first gate electrode layer.
22. The method of claim 21 , wherein the first conductivity type is N type, the first high-k dielectric comprises lanthanum oxide, the second conductivity type is P-type, and the second high-k dielectric comprises aluminum oxide.
23. The method of claim 21 , wherein the removing the first gate dielectric layer occurs after the forming the first gate electrode layer.