Flip-chip structure and method for high quality inductors and transformers
View Patent ↗A structure and method for achieving a flip-chip semiconductor device having plated copper inductors ( 4 ), transformers ( 16 ), interconnect, and power busing that is electrically superior, lower cost, and provides for higher quality inductors as well as lower losses for on-chip transformers. Providing a solder dam ( 8, 24, 28 ) enables the fabrication of flip-chip solder bumps directly on to inductors and transformers.
1. A process for fabricating a flip-chip structure, comprising the steps of:
depositing a barrier metal seed layer onto a metal bond pad formed on a wafer;
depositing a copper seed layer on said barrier metal seed layer;
electroplating an RF component on said copper seed layer;
depositing a dielectric layer over said RF component;
patterning said dielectric layer to expose a portion of said RF component;
applying a solder mask over said dielectric layer;
patterning a window in said solder mask over said the exposed portion of said RF component;
applying a solder material into said window and down to the exposed portion of said RF component;
reflowing said solder material into a solder bump; and
stripping said solder mask.
2. The process of claim 1 , wherein said solder material is applied through a squeegee process.
3. The process of claim 2 , wherein said solder material is a solder paste.
4. The process of claim 1 , further comprising the step forming sloping side walls on the exposed portion of said dielectric layer.
5. The process of claim 4 , wherein said sloping side walls are formed through a non-selective etch process.
6. The process of claim 1 , further comprising the steps of:
depositing a photoresist layer over said copper seed layer;
patterning a component window in said photoresist layer to receive said RF component.
7. The process of claim 1 , further comprising the step of etching the portions of said copper seed layer and said barrier metal seed layer not under said RF component off said wafer.
8. A process for forming a flip-chip solder bump on a wafer, comprising the steps of:
depositing a dielectric layer over an RF component formed on said wafer;
forming said dielectric layer into a solder dam through the steps of;
patterning said dielectric layer with a photolithographic process; and
performing a non-selective etch on said dielectric layer to form said solder dam with a sloped wall; and
applying a solder mask over said dielectric layer;
patterning said solder mask to form a window over said solder dam;
applying a solder paste to said wafer through a squeegee process;
reflowing said solder paste into said flip chip solder bump through a thermal process; and
stripping said solder mask.
9. The process of claim 8 , further comprising the step of inhibiting the flow of said solder paste with said solder dam.
10. The process of claim 9 , further comprising the step of forming said solder paste into a solder bump with said sloping side walls of said solder dam.
11. The process of claim 8 , further comprising the step of sealing said wafer with said dielectric layer.