Method for forming a multi-bit non-volatile memory device
View Patent ↗Forming a non-volatile memory device includes providing a semiconductor substrate, forming a masking layer having a first plurality of openings overlying the semiconductor substrate, forming diffusion regions in the semiconductor substrate at locations determined by the masking layer, forming a dielectric within the first plurality of openings, removing the masking layer to form a second plurality of openings, forming sacrificial spacers along edges of the second plurality of openings and adjacent to the dielectric, forming a separating dielectric to separate the sacrificial spacers within each of the second plurality of openings, forming a sacrificial protection layer overlying the separating dielectric, removing the sacrificial spacers, removing the sacrificial protection layer, forming at least two memory storage regions within each of the second plurality of openings, and forming a common control electrode overlying the at least two memory storage regions. This device may be used, for example, in a VGA memory array.
1. A method for forming a non-volatile memory device, comprising:
providing a semiconductor substrate;
forming a masking layer having a first plurality of openings overlying the semiconductor substrate;
forming diffusion regions in the semiconductor substrate at locations determined by the masking layer;
forming a dielectric within the first plurality of openings;
removing the masking layer to form a second plurality of openings;
forming sacrificial spacers along edges of the second plurality of openings and adjacent to the dielectric;
forming a separating dielectric to separate the sacrificial spacers within each of the second plurality of openings;
forming a sacrificial protection layer overlying the separating dielectric;
removing the sacrificial spacers;
removing the sacrificial protection layer;
forming at least two memory storage regions within each of the second plurality of openings; and
forming a common control electrode overlying the at least two memory storage regions.
2. The method of claim 1 further comprising:
forming a threshold voltage adjust implant region in the semiconductor substrate and between two adjacent sacrificial spacers within at least a predetermined one of the second plurality of openings.
3. The method of claim 1 further comprising:
forming the sacrificial spacers with disposable nitride or oxide sidewall spacers.
4. The method of claim 1 further comprising: forming the at least two memory storage regions with at least one selected from a group consisting of a plurality of nanoclusters, nitride traps, oxide traps, metal or polysilicon floating gates or a combination thereof.
5. The method of claim 1 wherein the sacrificial protection layer further comprises one of nitride or polysilicon.
6. The method of claim 1 further comprising forming an array of memory devices having a plurality of the memory device as recited in claim 1 .
7. The method of claim 1 wherein the separating dielectric comprises one of an oxide or a low dielectric constant material.
8. The method of claim 1 further comprising:
thinning the sacrificial protection layer to expose a portion of the sacrificial spacers before removing the sacrificial spacers.
9. The method of claim 8 wherein the thinning of the sacrificial protection layer further comprises one of etching or polishing.
10. The method of claim 1 wherein forming the at least two memory storage regions within each of the second plurality of openings further comprise forming a substantially continuous layer of discrete storage elements overlying the separating dielectric within at least a portion of the second plurality of openings.
11. The method of claim 10 further comprising forming nanoclusters as the continuous layer of discrete storage elements.
12. A method for forming a non-volatile memory device, comprising:
providing a semiconductor substrate;
forming a masking layer having a plurality of openings overlying the semiconductor substrate;
forming a first plurality of sacrificial spacers along edges of the plurality of openings;
forming a separating dielectric to separate the first plurality of sacrificial spacers within each of the plurality of openings;
forming a sacrificial protection layer overlying the separating dielectric;
removing the first plurality of sacrificial spacers;
removing the sacrificial protection layer;
forming a layer of memory storage material;
forming a second plurality of spacers along edges of the first plurality of openings, the second plurality of spacers overlying a portion of the layer of memory storage material to form at least two memory storage regions within each of the plurality of openings;
removing the layer of memory storage material from areas not underlying the second plurality of spacers;
forming a common control electrode between and overlying the at least two memory storage regions; and
forming diffusion regions within the semiconductor substrate and adjacent the common control electrode.
13. The method of claim 12 further comprising:
forming a threshold voltage adjust implant region in the semiconductor substrate and between two adjacent sacrificial spacers within at least a predetermined one of the plurality of openings.
14. The method of claim 12 further comprising:
forming the first plurality of sacrificial spacers with disposable nitride or oxide sidewall spacers.
15. The method of claim 12 further comprising: forming the layer of memory storage material with at least one selected from a group consisting of a plurality of nanoclusters, nitride traps, oxide traps, metal or polysilicon floating gates or a combination thereof.
16. The method of claim 12 wherein the sacrificial protection layer further comprises one of nitride or polysilicon.
17. The method of claim 12 further comprising forming an array of memory devices having a plurality of the non-volatile memory device as recited in claim 12 .
18. The method of claim 12 wherein the separating dielectric comprises one of an oxide or a low dielectric constant material.
19. The method of claim 12 further comprising:
thinning the sacrificial protection layer to expose a portion of the first plurality of sacrificial spacers before removing the first plurality of sacrificial spacers.
20. The method of claim 19 wherein the thinning of the sacrificial protection layer further comprises one of etching or polishing.
21. A method of forming a data storage device comprising:
providing a semiconductor substrate;
forming a sacrificial oxide overlying the semiconductor substrate;
forming a masking material overlying the sacrificial oxide, the masking material having a plurality of openings;
forming diffusion regions in the semiconductor substrate in areas underlying the plurality of openings of the masking material;
forming a dielectric adjacent the masking material and substantially filling the plurality of openings;
removing the masking material and forming disposable sidewall spacers adjacent edges of the dielectric;
forming a separating dielectric to separate the disposable sidewall spacers within each of the plurality of openings;
forming a sacrificial protection layer overlying the separating dielectric, the sacrificial protection being processed to leave a portion of the disposable sidewall spacers exposed;
removing the disposable sidewall spacers;
removing the sacrificial protection layer;
forming at least two memory storage regions within each of the plurality of openings; and
forming a common control electrode overlying the at least two memory storage regions.