System and method for reducing current in a device during testing
View Patent ↗A system ( 28 ) includes a microelectronic device ( 10 ) including first transistors ( 22 ) and second transistors ( 24 ), a power supply ( 40 ) electrically connected to the first and second transistors to provide power to the first and second transistors such that current flows through the first and second transistors, a switch ( 32 ) in operable communication with the second transistors, the switch allowing current to flow from the power supply through the second transistors when in a first mode of operation and preventing current from flowing from the power supply through the second transistors when in a second mode of operation, control circuitry in operable communication with the switch, and current sensing circuitry coupled to the first transistors to detect a test amount of current flowing through at least one of the first transistors when the switch is in the first mode of operation.
1. A system comprising:
a microelectronic device including first transistors and second transistors;
a power supply electrically connected to the first and second transistors to provide power to the first and second transistors such that current flows through the first and second transistors;
a switch in operable communication with the second transistors, the switch allowing current to flow from the power supply through the second transistors when in a first mode of operation and preventing current from flowing from the power supply through the second transistors when in a second mode of operation;
control circuitry in operable communication with the switch;
current sensing circuitry coupled to the first transistors to detect a test amount of current flowing through at least one of the first transistors when the switch is in the first mode of operation; and
a processor coupled to the current sensing circuitry and configured to calculate a reduced amount of current flowing through the first transistors when the switch is in the first mode of operation based on the test amount of current and calculate a combined amount of current flowing through the first and second transistors when the switch is in the second mode of operation based on the reduced amount of current.
2. The system of claim 1 , wherein the test amount of current is a predetermined percentage of the reduced amount of current and the reduced amount of current is a predetermined percentage of the combined amount of current.
3. The system of claim 1 , wherein the test amount of current, the reduced amount of current, and the combined amount of current are control currents for the at least one of the first transistors, the first transistors, and the first and second transistors, respectively.
4. The system of claim 1 , wherein the microelectronic device comprises a plurality of transistors, the first transistors are less than 50 percent of the plurality of transistors, and the at least one of the first transistors is less than 10 percent of the first transistors.
5. The system of claim 4 , wherein the test amount of current is less than 50 percent of the combined amount of current.
6. The system of claim 4 , wherein the first transistors are less than 25 percent of the plurality of transistors.
7. The system of claim 4 , wherein the at least one of the first transistors is less than 2 percent of the plurality of transistors.
8. The system of claim 4 , wherein the microelectronic device is a power integrated circuit and includes a microelectronic die, the plurality of transistors being formed on the microelectronic die.
9. A system for testing an electronic device having first transistors and second transistors, the system comprising:
a power supply electrically connectable to the first and second transistors to provide power to the first and second transistors such that current flows through the first and second transistors;
a switch to allow current to flow from the power supply through the second transistors when in a first mode of operation and prevent current from flowing from the power supply through the second transistors when in a second mode of operation;
control circuitry in operable communication with the switch;
current sensing circuitry coupled to the first transistors to detect a test amount of current flowing through at least one of the first transistors when the switch is in the first mode of operation; and
a processor coupled to the current sensing circuitry and configured to calculate a reduced amount of current flowing through the first transistors when the switch is in the first mode of operation based on the test amount of current and to calculate a combined amount of current flowing through the first and second transistors when the switch is in the second mode of operation based on the reduced amount of current.
10. The system of claim 9 , wherein the test amount of current is a predetermined percentage of the reduced amount of current and the reduced amount of current is a predetermined percentage of the combined amount of current.
11. The system of claim 9 , wherein the test amount of current, the reduced amount of current, and the combined amount of current are control currents for the at least one of the first transistors, the first transistors, and the first and second transistors, respectively.
12. The system of claim 9 , wherein the microelectronic device comprises a plurality of transistors, the first transistors are less than 50 percent of the plurality of transistors, and the at least one of the first transistors is less than 10 percent of the of the first transistors.
13. The system of claim 12 , wherein the test amount of current is less than 50 percent of the combined amount of current, the first transistors are less than 25 percent of the plurality of transistors, and the at least one of the first transistors is less than 2 percent of the plurality of transistors.
14. A system comprising:
a microelectronic device comprising a plurality of transistors including first transistors and second transistors, the first transistors being less than 50 percent of the plurality of transistors;
a power supply electrically connected to the first and second transistors to provide power to the first and second transistors such that current flows through the first and second transistors;
a switch in operable communication with the second transistors, the switch allowing current to flow from the power supply through the second transistors when in a first mode of operation and preventing current from flowing from the power supply through the second transistors when in a second mode of operation;
control circuitry in operable communication with the switch;
current sensing circuitry coupled to the first transistors to detect a test amount of current flowing through at least one of the first transistors when the switch is in the first mode of operation, the at least one of the first transistors being less than 10 percent of the first transistors; and
a processor coupled to the current sensing circuitry and configured to calculate a reduced amount of current flowing through the first transistors when the switch is in the first mode of operation based on the test amount of current and to calculate a combined amount of current flowing through the first and second transistors when the switch is in the second mode of operation based on the reduced amount of current.
15. The system of claim 14 , wherein the test amount of current is a predetermined percentage of the reduced amount of current and the reduced amount of current is a predetermined percentage of the combined amount of current.
16. The system of claim 15 , wherein the test amount of current, the reduced amount of current, and the combined amount of current are control currents for the at least one of the first transistors, the first transistors, and the first and second transistors, respectively.
17. The system of claim 16 , wherein the test amount of current is less than 50 percent of the combined amount of current, the first transistors are less than 25 percent of the plurality of transistors, and the at least one of the first transistors is less than 2 percent of the plurality of transistors.
18. The system of claim 17 , wherein the microelectronic device is a power integrated circuit and includes a microelectronic die, the plurality of transistors being formed on the microelectronic die.