Low voltage NMOS-based electrostatic discharge clamp
View Patent ↗Systems and methods are described for a low-voltage electrostatic discharge clamp. A resistor pwell-tied transistor may be used as a low-voltage ESD clamp, where the body of the transistor is coupled to the source by a resistor, thereby reducing a DC leakage current and minimizing latch-ups in the transistor while maintaining effective ESD performance.
1. A resistor p-well connected transistor comprising:
a substrate;
an isolating structure in the substrate;
an isolating layer adjacent to the isolating structure;
a well adjacent to the isolating layer and the isolating structure;
a first doped region in the well;
a first conducting terminal adjacent to the first doped region defining a body;
a second doped region in the well;
a second conducting terminal adjacent to the second doped region defining a source, the source being connected to a ground potential;
a dielectric layer adjacent to the well;
a third conducting terminal adjacent to the dielectric layer defining a gate;
a third doped region in the well;
a fourth conducting terminal adjacent to the third doped region defining a drain, the drain being connected to a node of a circuit under protection; and
a resistive element coupled between the first conducting terminal and the second conducting terminal.
2. The resistor p-well connected transistor of claim 1 , the resistive element comprising a resistor.
3. The resistor p-well connected transistor of claim 1 , the resistive element comprising a semiconductor switch configured as a resistor.
4. The resistor p-well connected transistor of claim 3 , the semiconductor switch comprising:
a switch drain connected to the body;
a switch source connected to the source; and
a switch gate connected to a voltage supply.
5. The resistor p-well connected transistor of claim 1 , the substrate comprising a p-type substrate.
6. The resistor p-well connected transistor of claim 1 , the isolating structure comprising a n-type well.
7. The resistor p-well connected transistor of claim 1 , the isolating structure comprising a n-well ring.
8. The resistor p-well connected transistor of claim 1 , the isolating structure comprising a deep trench isolation structure.
9. The resistor p-well connected transistor of claim 1 , the isolating layer comprising a n-type layer.
10. The resistor p-well connected transistor of claim 1 , the well comprising a p-well.
11. The resistor p-well connected transistor of claim 1 , the first region comprising a p+ doped region.
12. The resistor p-well connected transistor of claim 1 , the second region comprising a n+ doped region.
13. The resistor p-well connected transistor of claim 1 , the third region comprising a n+ doped region.
14. The resistor p-well connected transistor of claim 1 , the second and third conducting terminals being adjacent to each other.
15. The resistor p-well connected transistor of claim 1 , the first, the second, the third, and the fourth conducting terminals comprising metal terminals.