Microprocessor and method for register addressing therein
View Patent ↗A microprocessor architecture comprising a microprocessor operably coupled to a plurality of registers and arranged to execute at least one instruction. The microprocessor is arranged to determine a class of data operand. The at least one instruction comprises one or more codes in a register specifier that indicates whether relative addressing or absolute addressing is used in accessing a register. In this manner, absolute and relative register addressing is supported within a single instruction word.
1. A microprocessor architecture comprising:
a microprocessor including a plurality of registers that are internal to the microprocessor, the microprocessor arranged to execute a plurality of instructions that each use a respective first operand of a first operand class, and a respective second operand of a second operand class, each instruction of the plurality of instructions having a respective opcode that comprises:
a first field that indicates whether a first register address where its first operand is stored is to be determined using absolute addressing or using relative addressing with respect to an address of a previously accessed register of the first operand class; and
a second field that indicates whether a second register address where its second operand is stored is to be determined using absolute addressing or using relative addressing with respect to an address of a previously accessed register of the second operand class.
2. The microprocessor architecture of claim 1 wherein the one or more bit fields comprises an n-bit code used as a register specifier (RSPEC).
3. The microprocessor architecture according to claim 2 wherein one or more codes of the register specifier is/are reserved to support relative register addressing.
4. The microprocessor architecture according to claim 2 wherein the register specifier specifies another address relative to a last address accessed in a register array.
5. The microprocessor architecture according to claim 4 wherein specifying an address relative to the last address accessed comprises wrapping addresses to a first address or the last address in the register array.
6. The microprocessor architecture according to claim 1 wherein the class of operand encompasses one or more of the following: source-1, source-2, and destination.
7. An integrated circuit comprising the microprocessor architecture according to claim 1 .
8. The microprocessor architecture according to claim 1 further comprising:
a first register associated with the first operand class, the first register to store the address of the previously accessed register of the first operand class, wherein the address of the previously accessed register of the first operand class stored in the first register is updated only by operands of the first operand class; and
a second register associated with the second operand class, the second register to store the address of the previously accessed register of the second operand class, wherein the address of the previously accessed register of the second operand class stored in the second register is updated only by operands of the second operand class.
9. A method for register addressing in a microprocessor architecture comprising a microprocessor including a plurality of registers that are internal to the microprocessor, the method comprising:
executing at least one instruction that each of the at least one instruction uses or generates a respective plurality of data operands including a respective first operand of a first operand class and a respective second operand of a second operand class;
determining based upon a respective first one or more bits of the instruction whether relative addressing or absolute addressing is used to determine register addresses, of the plurality of registers, for operands of the first operand class; and
determining based upon a respective second one or more bits of the instruction whether relative addressing or absolute addressing is used to determine register addresses, of the plurality of registers, for operands of the second operand class.
10. The method for register addressing of claim 9 wherein the one or more bits comprises an n-bit code used as a register specifier (RSPEC).
11. The method for register addressing according to claim 10 wherein the register specifier specifies another address relative to a last address accessed in a register array.
12. The method for register addressing according to claim 11 wherein specifying the another address relative to the last address accessed comprises wrapping addresses to a first address or the last address in the register array.
13. The method for register addressing according to claim 11 wherein specifying an address relative to the last address accessed comprises wrapping addresses to a first address or the last address in the register array.
14. The method for register addressing according to claim 10 further comprising: reserving one or more codes in the register specifier in an opcode word to support relative register addressing.
15. The method for register addressing according to claim 9 further comprising: reserving one or more codes in a register specifier in an opcode word to support relative register addressing.
16. The method for register addressing according to claim 15 wherein the register specifier specifies another address relative to a last address accessed in a register array.
17. The method for register addressing according to claim 15 wherein the class of operand encompasses one or more of the following: source-1, source-2, and destination.
18. The method for register addressing according to claim 9 wherein the class of operand encompasses one or more of the following: source-1, source-2, and destination.
19. A method for register addressing in a microprocessor architecture comprising a microprocessor including a plurality of registers that are internal to the microprocessor, the method comprising:
executing an instruction that uses a plurality of data operands including a first operand of a first operand class and a second operand of a second operand class;
determining based upon a first one or more bits of the instruction whether absolute addressing or relative addressing with respect to an address of a previously accessed register of the first operand class is used for a first register address where the first operand is stored; and
determining based upon a second one or more bits of the instruction whether absolute addressing or relative addressing with respect to an address of a previously accessed register of the second operand class is used for a second register address where the second operand is stored.
20. The method of claim 19 wherein specifying an address relative to the last address accessed comprises wrapping addresses to a first address or the last address in the register array.