IP Library Granted Patent US 7,101,736
Granted Patent B2
US 7,101,736 · App. 10/891,648 · Granted Sep 5, 2006

Method of assembling a semiconductor component and apparatus therefor

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Quick Facts
Patent No.
US 7,101,736
App. No.
10/891,648
Granted
Sep 5, 2006
Kind
B2
Abstract

A method of assembling a semiconductor component includes providing a pedestal, placing a first piece on the curved pedestal, wherein the first piece comprises a semiconductor die, placing a second piece over the first piece, and providing an adhesive between the first piece and the second piece. The method further includes applying pressure with a first plate to the first piece and second piece to snap the first piece with the second piece, and applying heat with a second plate to reflow the adhesive, wherein applying heat is performed simultaneously with applying pressure.

Claims (56)

1. A method of assembling a semiconductor component, the method comprising:

providing a curved pedestal, wherein the curved pedestal has a concave portion;

placing a first piece on the concave portion of the curved pedestal, wherein the first piece comprises a semiconductor die;

placing a second piece over the first piece;

providing an adhesive between the first piece and the second piece;

applying pressure with a first plate to the first piece and second piece to snap the first piece with the second piece; and

applying heat with a second plate to reflow the adhesive, wherein applying heat is performed simultaneously with applying pressure.

2. The method of claim 1 , further comprising:

aligning the first piece to the second piece with alignment features, wherein the alignment features are part of the plate.

3. The method of claim 1 , further comprising:

aligning the first piece to the second piece with alignment features, wherein the alignment features are part of the first piece.

4. The method of claim 1 , wherein providing a curved pedestal comprises:

providing a first curved pedestal;

placing a first piece on the curved pedestal, wherein the first piece comprises a first semiconductor die;

placing a second piece over the first piece;

providing an adhesive between the first piece and the second piece;

applying pressure with a first plate to the first piece and second piece to snap the first piece with the second piece; and

applying heat with a second plate to reflow the adhesive and form a test semiconductor component, wherein applying heat is performed simultaneously with applying pressure;

measuring the topography of the test semiconductor component,

comparing the topography of the test semiconductor component to a predetermined topography; and

choosing a second curved pedestal, wherein the second curved pedestal has a different curvature than the first curved pedestal; and

providing the second curved pedestal.

5. The method of claim 4 , wherein

placing a first piece on the curved pedestal further comprises placing a first piece, wherein the first piece further comprises a flange;

placing a second piece over the first piece further comprises placing a second piece, wherein the second piece comprises an insulator;

providing an adhesive further comprises providing an adhesive, wherein the adhesive further comprises a solder perform.

6. The method of claim 1 , wherein placing a second piece over the first piece further comprises placing a second piece, wherein the second piece further comprises leads.

7. The method of claim 1 , wherein

applying pressure with a first plate further comprises applying pressure from the top of the second piece; and

applying heat with a second plate further comprises applying heat from the bottom of the first piece.

8. The method of claim 1 , further comprising placing a third piece over the first piece, wherein the third piece comprises leads.

9. A method of forming a semiconductor component, the method comprising:

providing a heat plate with a cavity;

placing a curved pedestal in the cavity;

placing a flange comprising a semiconductor die on the curved pedestal;

placing solder on the flange;

placing a window frame over the solder;

moving an alignment header down and in contact with the window frame and the flange,

wherein the alignment header comprises alignment features that secure alignment of the flange to the window frame;

applying pressure with the alignment header to the first window frame and the flange;

applying heat with the heat plate to reflow the solder to couple the flange, solder and window frame.

10. The method of claim 9 , wherein placing the window frame over the solder comprises placing the window frame, wherein the window frame comprises leads.

11. The method of claim 9 , wherein

applying pressure further comprises applying pressure from the top of the window frame; and

applying heat further comprises applying heat from the bottom of the flange.

12. The method of claim 9 , wherein providing a curved pedestal comprises:

providing a first curved pedestal;

placing a first piece on the curved pedestal, wherein the first piece comprises a first semiconductor die;

placing a second piece over the first piece;

providing an adhesive between the first piece and the second piece;

applying pressure with a first plate to the first piece and second piece to snap the first piece with the second piece; and

applying heat with a second plate to reflow the adhesive and form a test semiconductor component, wherein applying heat is performed simultaneously with applying pressure;

measuring the topography of the test semiconductor component;

comparing the topography of the test semiconductor component to a predetermined topography; and

choosing a second curved pedestal, wherein the second curved pedestal has a different curvature than the first curved pedestal; and

providing the second curved pedestal.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
RE-RECORD TO CORRECT THE SECOND ASSIGNOR'S FIRST NAME ON A DOCUMENT PREVIOUSLY RECORDED AT REEL 015639, FRAME 0816. (ASSIGNMENT OF ASSIGNOR'S INTEREST) Recorded Jun 13, 2005
From: SANCHEZ, AUDEL A.; KIM, TAEK K.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 016680/0716 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2004
From: SANCHEZ, AUDEL A.; KIM, TEAK K.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 015639/0816 →