Variable impedance output buffer
View Patent ↗An output buffer circuit ( 10, 40, 50 ) includes an output driver transistor ( 12 ), a predriver circuit ( 14, 54 ), and a bias generator ( 16, 54 ). The predriver circuit ( 14, 54 ) has an input terminal for receiving an input signal (IN), a first terminal coupled to a power supply voltage terminal, a second terminal, and an output terminal coupled to the control electrode of the transistor ( 12 ). The bias generator ( 16, 54 ) is coupled to the second terminal of the predriver circuit ( 14, 54 ), and provides a bias voltage (V G ) to the second terminal of the predriver circuit ( 14, 54 ) for controlling the gate voltage of the output driver transistor ( 12 ).
1. An output buffer circuit comprising:
an output driver transistor having a first current electrode coupled to a power supply voltage terminal, a control electrode, and a second current electrode for providing an output signal;
a predriver circuit having an input terminal for receiving an input signal, a first terminal coupled to the power supply voltage terminal, a second terminal, and an output terminal coupled to the control electrode of the output driver transistor;
a resistor having a first terminal coupled to the power supply voltage terminal, and a second terminal;
a first transistor having a first current electrode coupled to the second terminal of the resistor, a control electrode coupled to the second terminal of the predriver circuit, and a second current electrode; and
a second transistor having a first current electrode coupled to the second terminal of the resistor, a control electrode coupled to the second terminal of the predriver circuit, and a second current electrode.
2. The output buffer circuit of claim 1 , wherein the output driver transistor is biased to operate in a linear region for matching a characteristic impedance of a transmission line coupled to the second current electrode of the output driver transistor.
3. The output buffer circuit of claim 1 , wherein the predriver circuit comprises an inverter.
4. The output buffer circuit of claim 1 , wherein the first transistor is for tracking a predetermined characteristic of the output driver transistor.
5. The output buffer circuit of claim 1 , wherein the first transistor is substantially a scaled replica of the output driver transistor.
6. The output buffer circuit of claim 1 , wherein the second current electrode of the first transistor is coupled to the second current electrode of the output driver transistor.
7. The output buffer circuit of claim 1 , wherein the second current electrode of the first transistor is coupled to receive a reference voltage.
8. The output buffer circuit of claim 1 , wherein the second current electrode of the second transistor is coupled to a current source.
9. The output buffer circuit of claim 1 , wherein the second current electrode of the second transistor is coupled to the input terminal of the predriver circuit.
10. The output buffer circuit of claim 1 , further comprising a unity gain amplifier having an output terminal coupled to the second terminal of the predriver circuit.
11. An output buffer circuit comprising:
an output driver transistor having a first current electrode coupled to a power supply voltage terminal, a control electrode, and a second current electrode for providing an output signal;
a predriver circuit having an input terminal for receiving an input signal, a first terminal coupled to the power supply voltage terminal, a second terminal, and an output terminal coupled to the control electrode of the output driver transistor; and
a bias generator coupled to the second terminal of the predriver circuit, for providing a bias voltage to the second terminal of the predriver circuit for controlling the gate voltage of the output driver transistor, the bias generator comprising:
a resistor having a first terminal coupled to the power supply voltage terminal, and a second terminal;
a first transistor having a first current electrode coupled to the second terminal of the resistor, a control electrode coupled to the output terminal of the predriver circuit, and a second current electrode, wherein the first transistor is a substantially scaled replica of the output driver transistor; and
a second transistor having a first current electrode coupled to the second terminal of the resistor, a control electrode coupled to the output terminal of the predriver circuit, and a second current electrode.
12. The output buffer circuit o claim 11 , wherein the output driver transistor is biased to operate in an linear region for matching a characteristic impedance of a transmission line coupled to the second current electrode of the output driver transistor.
13. The output buffer circuit of claim 11 , wherein the second current electrode of the first transistor is coupled to the second current electrode of the output driver transistor for feeding back the output signal to the bias generator.
14. The output buffer circuit of claim 11 , wherein the second current electrode of the first transistor is coupled to receive a reference voltage.
15. The output buffer circuit of claim 11 , wherein the second current electrode of the second transistor is coupled to the output terminal of the predriver circuit.
16. The output buffer circuit of claim 11 , further comprising:
a current source having a first terminal coupled to the second terminal of the predriver circuit, and a second terminal coupled to a second power supply voltage terminal; and
a capacitive element having a first plate electrode coupled to the second terminal of the predriver circuit, and a second terminal coupled to the second power supply voltage terminal.