Capping layer for reducing amorphous carbon contamination of photoresist in semiconductor device manufacture; and process for making same
View Patent ↗In the fabrication of semiconductor devices using the PECVD process to deposit hardmask material such as amorphous carbon, structure and process are described for reducing migration of species from the amorphous carbon which can damage an overlying photoresist. In one embodiment useful to 248 nm and 193 nm photolithography exposure wavelengths, amorphous carbon is plasma-deposited on a substrate to pre-defined thickness and pre-defined optical properties. A SiON layer is combined with a silicon-rich oxide layer, a silicon-rich nitride layer or a TEOS layer to create a capping layer resistant to species-migration. Layers are formulated to pre-determined thicknesses, refractive indices and extinction coefficients. The capping stacks constitute an effective etch mask for the amorphous carbon; and the hardmask properties of the amorphous carbon are not compromised. The disclosure has immediate application to fabricating polysilicon gates.
1. An etch mask structure formed over a device layer during fabrication of a semiconductor device, said etch mask structure comprising:
a layer of amorphous carbon formed over said device layer;
a capping stack formed over said amorphous carbon layer;
and a photoresist film deposited over said capping stack;
said capping stack comprising
a deposition of SiON and
a deposition adjacent to said SiON deposition of a second material selected to retard migration of species of nitrogen and hydrogen from said SiON deposition to said photoresist layer.
2. An etch mask structure according to claim 1 , wherein said second material is silicon-rich nitride.
3. An etch mask structure according to claim 2 , wherein
said device layer is a polysilicon gate layer having a layer thickness of from 1000 Angstroms to 2000 Angstroms and
said silicon-rich nitride has a refractive index in a range of from 1.7 to 1.9 and an extinction coefficient in a range of from 0.25 to 0.35.
4. An etch mask structure according to claim 1 , wherein said second material is silicon-rich oxide.
5. An etch mask structure according to claim 4 , wherein
said device layer is a polysilicon gate layer having a layer thickness of from 1000 Angstroms to 2000 Angstroms and
said silicon-rich oxide has a refractive index in a range of from 1.50 to 1.85 and an extinction coefficient in a range of from 0.0 to 0.2.
6. An etch mask structure according to claim 1 , wherein said second material is TEOS.
7. An etch mask structure according to according to claim 6 wherein
said device layer is a polysilicon gate layer having a layer thickness of from 1000 Angstroms to 2000 Angstroms and
said TEOS has a refractive index in a range of from 1.60 to 1.74 and an extinction coefficient in a range of from 0.0 to 0.2.
8. An etch mask structure formed over a device layer during fabrication of a semiconductor device using PECVD deposition processes, said etch mask structure comprising:
a layer of amorphous carbon formed over said device layer;
a capping stack formed over said amorphous carbon layer;
and a photoresist film deposited over said capping stack;
said capping stack comprising
a deposition of SiON and
a deposition adjacent to said SiON deposition of a second material selected to retard migration of species of nitrogen and hydrogen from said SiON deposition to said photoresist layer.
9. For use during a semiconductor device fabrication process, an intermediate structure formed over a deposited amorphous carbon layer in said device to retard migration of species of nitrogen and hydrogen from said deposited layer to an overlaid photoresist layer, said intermediate structure comprising:
a capping stack formed over said deposited layer and comprising
a deposition of SiON and
a deposition adjacent to said SiON deposition of a second material selected from the group consisting of silicon-rich nitride, silicon-rich oxide and TEOS.
10. In the fabrication of a semiconductor device comprising a device layer formed on a substrate, an interconnect layer providing circuit accesses to said device layer, and an amorphous carbon layer formed atop said interconnect layer, a method for retarding migration of species of nitrogen and hydrogen to a photoresist layer formed to pattern said interconnect layer, said method comprising
forming a capping stack atop said amorphous carbon layer by
depositing a layer of SiON over said device layer; and
depositing adjacent to said SiON deposition a layer of a second material selected from the group consisting of silicon-rich nitride, silicon-rich oxide and TEOS.
11. The method of claim 10 wherein said second material is deposited beneath said layer of SiON.
12. The method of claim 10 wherein said second material is deposited atop said layer of SiON.
13. The method of claim 10 wherein
said device layer is a polysilicon gate layer having a layer thickness of from 1000 Angstroms to 2000 Angstroms and
the step of depositing said second material comprises depositing silicon-rich nitride and controlling deposition parameters to impart a refractive index in a range of from 1.7 to 1.9 and an extinction coefficient in a range of from 0.25 to 0.35.
14. The method of claim 10 wherein
said device layer is a polysilicon gate layer having a layer thickness of from 1000 Angstroms to 2000 Angstroms and
the step of depositing said second material comprises depositing silicon-rich oxide and controlling deposition parameters to impart a refractive index in a range of from 1.50 to 1.85 and an extinction coefficient in a range of from 0.0 to 0.2.
15. The method of claim 10 wherein
said device layer is a polysilicon gate layer having a layer thickness of from 1000 Angstroms to 2000 Angstroms and
the step of depositing said second material comprises depositing TEOS and controlling deposition parameters to impart a refractive index in a range of from 1.60 to 1.74 and an extinction coefficient in a range of from 0.0 to 0.2.